Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same

A method of fabricating a semiconductor device on a semiconductor substrate having a first region and a second region, the method comprising the steps of:

• forming a channel layer comprising a compressively-stressed semiconductor material overlying the second region of the semiconductor substrate;
• forming a high dielectric constant layer overlying the first region of the semiconductor substrate and the channel layer;
• depositing a metal-comprising gate layer overlying the high dielectric constant layer;
• forming an in situ doped silicon capping layer overlying the metal-comprising gate layer;
• forming a silicide-forming metal capping layer;
• forming a silicon-comprising gate layer overlying the in situ doped silicon capping layer and the silicide-forming metal capping layer, wherein the silicide-forming metal capping layer is interposed between the in situ doped silicon capping layer and the silicon-comprising gate layer;
• and
• heating the substrate.

A semiconductor device having a gate stack overlying a semiconductor substrate, the gate stack comprising:

• a high dielectric constant layer disposed overlying the semiconductor substrate;
• a metal-comprising gate layer disposed overlying the high dielectric constant layer;
• a doped silicon capping layer disposed overlying the metal-comprising gate layer;
• a silicon-comprising gate layer overlying the doped silicon capping layer;
• and
• a silicide-forming metal capping layer interposed between the doped silicon-comprising capping layer and the silicon-comprising gate layer.

A method for forming a semiconductor device comprising a semiconductor substrate, wherein the method comprises the steps of:

• forming a high dielectric constant layer overlying the semiconductor substrate;
• forming a metal-comprising gate layer overlying the high dielectric constant layer;
• forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer;
• forming a silicide-forming metal capping layer overlying the doped silicon-comprising capping layer;
• and
• depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer, wherein the silicide-forming metal capping layer is interposed between the doped silicon-comprising capping layer and the silicon-comprising gate layer.

A semiconductor device having a gate stack overlying a semiconductor substrate, the gate stack comprising:

• a high dielectric constant layer disposed overlying the semiconductor substrate;
• a metal-comprising gate layer overlying the high dielectric constant layer;
• a doped silicon capping layer directly overlying and in contact with the metal-comprising gate layer;
• a silicide-forming metal capping layer;
• and
• a silicon-comprising gate layer directly overlying the silicide-forming metal capping layer.