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US 8,026,504 B2Granted
Semiconductor device and method of forming the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJun-Beom Park, Soon-Moon Jung, Ki-Nam Kim
Life of this patent
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Abstract
A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.
Claims14
A semiconductor device comprising:
- a semiconductor substrate having a cell array region and a peripheral circuit region;
- a common node on the semiconductor substrate in the cell array region and including resistive memory elements, the common node extending perpendicularly upward from the semiconductor substrate;
- first and second active elements electrically connected to the common node, extending from a sidewall of the common node, and sequentially stacked on the semiconductor substrate;
- and
- an insulating layer disposed on the semiconductor substrate, surrounding the common node and interposed between the first and second active elements, wherein the common node includes,
- a conductive plug;
- a bistable resistance pattern surrounding a sidewall and a bottom surface of the conductive plug;
- and
- buffer layers disposed on a sidewall of the bistable resistance pattern,
- wherein the resistive memory elements are disposed in the bistable resistance pattern adjacent to the buffer layer.
7 more elements
A unit memory cell array block comprising:
- a common node including a plurality of resistive memory elements;
- a first active element connected to one of the plurality of resistive memory elements at a lower region of the common node;
- a second active element connected to another one of the plurality of resistive memory elements at an upper region of the common node, and stacked on the first active element;
- an insulating layer surrounding the common node and interposed between the first and second active elements;
- a third active element connected to one of the plurality of resistive memory elements at other lower region, symmetrical to the first active element with respect to the common node;
- and
- a fourth active element connected to other one of the plurality of resistive memory elements at other upper region, symmetrical to the second active element with respect to the common node, wherein the common node includes,
- a conductive plug;
- a bistable resistance pattern surrounding a sidewall and a bottom surface of the conductive plug;
- and
- buffer layers disposed at contacting portion of the bistable resistance pattern and the each of the active elements,
- wherein the plurality of resistive memory elements are disposed in the bistable resistance pattern between the buffer layer and the conductive plug.
9 more elements
A semiconductor memory device comprising:
- a substrate having a cell array region and a peripheral circuit region;
- a common node on the substrate in the cell array region, and including a plurality of resistive memory elements;
- a first body region disposed on the substrate and including first active element connected to one of the plurality of resistive memory elements at a lower region of the common node;
- a second body region disposed on the first body region and including a second active element connected to another one of the plurality of resistive memory elements at an upper region of the common node, and stacked on the first active element;
- and
- an insulating layer disposed on the substrate, surrounding the common node and interposed between the first and second active elements, wherein the common node includes,
- a conductive plug;
- a bistable resistance pattern surrounding a sidewall and a bottom surface of the conductive plug;
- and
- buffer layers disposed on a sidewall of the bistable resistance pattern,
- wherein the resistive memory elements are disposed in the bistable resistance pattern adjacent to the buffer layer.
8 more elements
Dependencies are inferred from the claim text.