Semiconductor device and semiconductor device manufacturing method
AssigneeMitsubishi Electric Corporation
InventorsYoichiro Tarui, Ken-ichi Ohtsuka, Masayuki Imaizumi
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Abstract
In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers.
Claims10
A semiconductor device manufacturing method comprising:
- (A) forming an impurity layer having p type conductivity in a surface of a SiC region having n type conductivity;
- and
- (B) applying an ion implantation to said SiC region in a region adjacent to said impurity layer, so as to form a first Junction Termination Edge (JTE) layer adjacent to said impurity layer and having a lower impurity concentration than said impurity layer, said step (B) applying said ion implantation at varied energies such that said first JTE layer is formed from a first depth in said SiC region to a second depth that does not reach the surface of said SiC region.
A semiconductor device manufacturing method comprising:
- (A) forming an impurity layer having p type conductivity in a surface of a SiC region having n type conductivity;
- and
- (B) applying an ion implantation to said SiC region in a region adjacent to said impurity layer, so as to form a first Junction Termination Edge (JTE) layer adjacent to said impurity layer and having a lower impurity concentration than said impurity layer, said step (B) applying said ion implantation at varied energies to effect a p type ion implantation from a first depth in said SiC region to the surface of said SiC region, and then applying said ion implantation at varied energies to effect an n type ion implantation from the surface of said SiC region to a second depth of said SiC region, so as to form said first JTE layer.
A semiconductor device manufacturing method comprising:
- (a) forming a first impurity layer having p type conductivity in a surface of a SiC region having n type conductivity;
- (b) forming a first Junction Termination Edge (JTE) layer adjacent to said first impurity layer in the surface of said SiC region, said first JTE layer having a lower impurity concentration than said first impurity layer;
- (c) applying an epitaxial growth using a given dopant to form an epi-film having n type conductivity on an upper surface of said SiC region;
- and
- (d) removing a portion of said epi-film such that a second impurity layer having n type conductivity remains at least on said first JTE layer.
A semiconductor device manufacturing method comprising the:
- (a) forming a first impurity layer having p type conductivity in a surface of a SiC region having n type conductivity;
- (b) forming a first Junction Termination Edge (JTE) layer adjacent to said first impurity layer in the surface of said SiC region, said first JTE layer having a lower impurity concentration than said first impurity layer;
- (c) applying an epitaxial growth using a given dopant to form an epi-film having n type conductivity on an upper surface of said SiC region;
- (d) removing a portion of said epi-film such that a second impurity layer having n type conductivity remains at least on said first JTE layer;
- and
- (e) applying an n type ion implantation to said second impurity layer.
A semiconductor device manufacturing method comprising:
- (a) forming a first impurity layer having p type conductivity in a surface of a SiC region having n type conductivity;
- (b) forming a first Junction Termination Edge (JTE) layer adjacent to said first impurity layer in the surface of said SiC region, said first JTE layer having a lower impurity concentration than said first impurity layer;
- (c) applying an epitaxial growth using a given dopant to form an epi-film having p type conductivity on an upper surface of said SiC region;
- (d) removing a portion of said epi-film such that a second impurity layer having p type conductivity remains at least on said first JTE layer;
- and
- (e) applying an n type ion implantation to said second impurity layer to make said second impurity layer n type.
Dependencies are inferred from the claim text.