Method of fabricating semiconductor transistor devices with asymmetric extension and/or halo implants

A method of fabricating semiconductor devices, the method comprising:

• providing a device structure comprising a semiconductor material and a plurality of gate structures formed overlying the semiconductor material;
• creating light dose extension implants in the semiconductor material, using the plurality of gate structures as a first implantation mask, by bombarding the device structure with ions at a non-tilted angle relative to a reference surface of the semiconductor material;
• forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed;
• forming halo implants in the semiconductor material, using the plurality of gate structures and the patterned mask together as a second implantation mask, by bombarding the device structure with ions at a tilted angle relative to the reference surface of the semiconductor material, and toward the plurality of gate structures;
• and
• producing heavy dose extension implants in the semiconductor material, using the second implantation mask, by bombarding the device structure with ions at a second tilted angle relative to the reference surface of the semiconductor material, and toward the plurality of gate structures.

A method of fabricating a semiconductor device having adjacent transistor devices that share active regions, the method comprising:

• providing a device structure comprising a semiconductor material, a plurality of gate structures formed overlying the semiconductor material, a shared source region of the semiconductor material, which underlies a first space defined between a first gate structure of the plurality of gate structures and a second gate structure of the plurality of gate structures, and a shared drain region of the semiconductor material, which underlies a second space defined between the second gate structure and a third gate structure of the plurality of gate structures, the second gate structure being adjacent to the first gate structure, and the third gate structure being adjacent to the second gate structure;
• implanting a relatively light impurity dose into the semiconductor material while using the plurality of gate structures as a first implantation mask, resulting in light dose extension implants in the shared source region and in the shared drain region;
• protecting the shared drain region with a first patterned mask that leaves the shared source region substantially exposed;
• implanting a relatively high impurity dose into the semiconductor material while using the plurality of gate structures and the first patterned mask together as a second implantation mask, by bombarding the shared source region with ions of an impurity species at a first tilted angle and toward the second gate structure, resulting in a first heavy dose extension implant in the shared source region;
• and
• implanting another relatively high impurity dose into the semiconductor material while using the second implantation mask, by bombarding the shared source region with ions of the impurity species at a second tilted angle and toward the first gate structure, resulting in a second heavy dose extension implant in the shared source region.