Method of producing semiconductor
AssigneeUnisantis Electronics (Japan) Ltd.
InventorsFujio Masuoka, Shintaro Arai
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AssigneeUnisantis Electronics (Japan) Ltd.
InventorsFujio Masuoka, Shintaro Arai
Estimating the term…
In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a height dimension of the pillar-shaped silicon layer, and a gate length. In an SGT production method of the present invention, a hard mask for use in dry etching for forming a pillar-shaped silicon layer is formed in a layered structure comprising a first hard mask and a second hard mask, to allow the end-point detection process to be used during the dry etching for the pillar-shaped silicon layer. In addition, a gate conductive film for use in dry etching for forming a gate electrode is formed in a layered structure comprising a first gate conductive film and a second gate conductive film, to allow the end-point detection process to be used during the dry etching for the gate electrode.
A method of producing a semiconductor device in which a source diffusion layer, a drain diffusion layer and a pillar-shaped semiconductor layer are vertically arranged on an upper side of a substrate in a layered manner, and a gate is arranged around a sidewall of the pillar-shaped semiconductor layer, wherein the pillar-shaped semiconductor layer is arranged on a semiconductor substrate, the pillar-shaped semiconductor layer has a third protective film formed on a top thereof, and a dielectric film is arranged on respective surfaces of the semiconductor substrate and the pillar-shaped semiconductor layer, the method comprising the steps of:
A method of producing a semiconductor device in which a source diffusion layer, a drain diffusion layer and a pillar-shaped semiconductor layer are vertically arranged on an upper side of a substrate in a layered manner, and a gate is arranged around a sidewall of the pillar-shaped semiconductor layer, wherein the pillar-shaped semiconductor layer is arranged on a semiconductor substrate, the pillar-shaped semiconductor layer has a third protective film formed on a top thereof, and a dielectric film is arranged on respective surfaces of the semiconductor substrate and the pillar-shaped semiconductor layer, the method comprising the steps of:
Dependencies are inferred from the claim text.