Method for manufacturing semiconductor apparatus having saddle-fin transistor and semiconductor apparatus fabricated thereby

A semiconductor memory apparatus comprising:

• a unit cell including a saddle-fin transistor having a three-dimensional signal channel region as a cell transistor;
• and
• core and peripheral regions that include a multi-channel transistor having a three-dimensional multi-channel region,
• wherein a gate pattern included in each of the saddle-fin transistor and the multi-channel transistor includes a gate lower electrode that surrounds a side surface of a gate upper electrode, the upper portion of the gate lower electrode and the gate upper electrode are surrounded with a gate hard mask nitride film, and the lower portion of the gate lower electrode is surrounded with an oxide film.

A method for manufacturing a semiconductor memory apparatus, the method comprising:

• forming a device isolation film over a semiconductor substrate;
• forming a multi-channel region in core and peripheral regions through an etching process using a first multi-channel mask;
• forming a self-aligned hard mask in a cell region, the core and peripheral regions;
• simultaneously forming a channel region and a gate region in the cell region through a self-alignment etching process using the self-aligned hard mask;
• forming a gate region over the channel region in the core and peripheral regions through the self-alignment etching process and an etching process using a second multi-channel mask;
• and
• forming a gate pattern in the gate region of the cell, core and peripheral regions.