Recessed drain and source areas in combination with advanced silicide formation in transistors
AssigneeAdvanced Micro Devices, Inc.
InventorsUwe Griebenow, Andy Wei, Jan Hoentschel, Thilo Scheiper
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Abstract
During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency.
Claims18
A method, comprising:
- forming a spacer structure on sidewalls of a gate electrode of a transistor;
- exposing drain and source regions of said transistor and said gate electrode to an etch ambient to remove material at least from said gate electrode selectively to said spacer structure;
- forming a metal silicide material in said drain and source regions and said gate electrode after removing said material;
- and
- forming a strain-inducing layer above said gate electrode and said drain and source regions.
A method, comprising:
- performing an etch process to remove material from a first gate electrode of a first transistor and a second gate electrode of a second transistor and drain and source regions of at least one of said first and second transistors while protecting sidewalls of said first and second gate electrodes by a spacer structure;
- and
- forming a metal silicide in said first and second gate electrodes and said drain and source regions in the presence of said spacer structure, said metal silicide terminating in a doped silicon material of said first and second gate electrodes.
Dependencies are inferred from the claim text.