Device and process for heating III-V wafers, and annealed III-V semiconductor single crystal wafer

A process for heat treating at an increased temperature a wafer comprising, at least at a surface thereof, a semiconductor material comprising GaAs, the wafer having a diameter of ≧100 mm, wherein the process comprises:

• placing one or more wafers having a diameter of ≧100 mm in an interior space of a heating furnace or container;
• heating the wafer at an increased temperature without applying As partial pressure from the outside, such that precipitates of the As component are substantially reduced in size and/or density in a surface layer of the GaAs semiconductor material-comprising surface of the wafer,
• wherein the precipitates reduced in size and/or density in said surface layer are defined by a lpd value of lower than about 50 cm-2 (precipitate size range of 0.2-2 μm).

A process for heat treating at an increased temperature a wafer comprising, at least at a surface thereof, a semiconductor material comprising GaAs, wherein the process comprises:

• providing a wafer comprising, at least at a surface thereof, the GaAs semiconductor material, the wafer having a diameter of ≧100 mm,
• heating the wafer at an increased temperature, under a condition that extracts As from a region of the GaAs-comprising surface, thereby reducing density and/or size of As-precipitates in the surface region, the surface region being at least about 5 μm or more in thickness.

A process for heat treating at an increased temperature a wafer comprising a GaAs semiconductor material, comprising the steps of:

• providing a wafer having a diameter of ≧100 mm and comprising said GaAs semiconductor material at least at a surface thereof,
• heating the wafer at an increased temperature, under a condition wherein said GaAs semiconductor material-comprising wafer is either directly covered by a material that is gas-permeable, or is covered by a material positioned above said surface of the wafer at a distance of more than 0 mm and up to about 2 mm, such that precipitates of the As component are reduced in size and/or density in a surface layer of the GaAs semiconductor material-comprising surface of the wafer.