Distributed computing

An apparatus comprising:

• a first substrate for supporting a plurality of dual-chip carriers, the first substrate having first and second sides;
• a plurality of dual-chip carriers disposed on the first side of the first substrate, each dual-chip carrier comprising:
• a first conductive tray having a planar inner surface and a sidewall extending from the planar inner surface, the planar inner surface configured to receive and provide an electrical ground connection to a first integrated circuit die;
• and
• a second conductive tray having a planar inner surface and a sidewall extending from the planar inner surface, the planar inner surface configured to receive and provide an electrical ground connection to a second integrated circuit die, wherein once assembled the first die and second die are disposed facing one another, and wherein the respective sidewalls of the first and second conductive trays mate so as to make contact and also provide at least one gap through which a signal lead can extend;
• at least one electrical ground tab connectable to at least one of the first and second conductive trays and also connectable to at least one of the first die or the second die;
• at least one signal tab extending through a respective gap between the respective sidewalls of the first and second conductive trays;
• and
• at least one power line enveloped by an insulator abutting the first and second conductive trays, the at least one power line including at least one contact connectable to at least one of the first die or the second die.