Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level

An integrated circuit device as recited in 18, wherein a region within the gate electrode level between the gate electrode of the second transistor of the first transistor type and the gate electrode of the fourth transistor of the first transistor type is devoid of a conductive structure that physically contacts an underlying diffusion region, and wherein the second and fourth transistors of the first transistor type are formed to share a fourth diffusion region of the first diffusion type.

An integrated circuit device as recited in 18, wherein a region within the gate electrode level between the gate electrode of the second transistor of the second transistor type and the gate electrode of the fourth transistor of the second transistor type is devoid of a conductive structure that physically contacts an underlying diffusion region, and wherein the second and fourth transistors of the second transistor type are formed to share a third diffusion region of the second diffusion type.

An integrated circuit device as recited in 18, wherein a region within the gate electrode level between the gate electrode of the first transistor of the second transistor type and the gate electrode of the third transistor of the second transistor type is devoid of a conductive structure that physically contacts an underlying diffusion region, and wherein the first and third transistors of the second transistor type are formed to share a third diffusion region of the second diffusion type.

An integrated circuit device as recited in 21, wherein a region within the gate electrode level between the gate electrode of the second transistor of the first transistor type and the gate electrode of the fourth transistor of the first transistor type is devoid of a conductive structure that physically contacts an underlying diffusion region, and wherein the second and fourth transistors of the first transistor type are formed to share a fourth diffusion region of the first diffusion type.

An integrated circuit device as recited in 22, wherein a region within the gate electrode level between the gate electrode of the second transistor of the second transistor type and the gate electrode of the fourth transistor of the second transistor type is devoid of a conductive structure that physically contacts an underlying diffusion region, and wherein the second and fourth transistors of the second transistor type are formed to share a fourth diffusion region of the second diffusion type.

An integrated circuit device as recited in 17, wherein each of the first, second, third, and fourth transistors of the first transistor type is defined to have a respective first dimension as measured in the first direction,

• wherein the first dimension of the first transistor of the first transistor type is greater than the first dimension of the second transistor of the first transistor type.

An integrated circuit device as recited in 24, wherein the first dimension of the third transistor of the first transistor type is substantially equal to the first dimension of the first transistor of the first transistor type, and

• wherein the first dimension of the fourth transistor of the first transistor type is substantially equal to the first dimension of the second transistor of the first transistor type.

An integrated circuit device as recited in 24, wherein each of the first, second, third, and fourth transistors of the second transistor type is defined to have a respective first dimension as measured in the first direction,

• wherein the first dimension of the first transistor of the second transistor type is greater than the first dimension of the second transistor of the second transistor type.

An integrated circuit device as recited in 26, wherein the first dimension of the third transistor of the second transistor type is substantially equal to the first dimension of the first transistor of the second transistor type, and

• wherein the first dimension of the fourth transistor of the second transistor type is substantially equal to the first dimension of the second transistor of the second transistor type.