Back to results
US 8,021,989 B2Granted
Method for high topography patterning
AssigneeImec
InventorsStaf Verhaegen, Axel Nackaerts
Life of this patent
Estimating the term…
Abstract
One inventive aspect is related to a method for isolating structures of a semiconductor material, comprising providing a pattern of the semiconductor material comprising at least one elevated line, defining device regions in the pattern, the device regions each comprising at least said at least one elevated line, and modifying the conductive properties of the semiconductor material outside said device regions, such that the device regions are electrically isolated.
Claims12
A method of isolating structures of a semiconductor material, the method comprising:
- providing a pattern of the semiconductor material comprising an elevated line;
- defining two device regions in the pattern, the device regions being separated by an isolation region in the pattern located between the device regions wherein each device region comprises a region in which a FinFET is to be formed, wherein the isolation region electrically connects the device regions to each other, wherein the elevated line has a portion in each of the device regions and the isolation region;
- and
- after providing a pattern of the semiconductor material and defining device regions in the pattern, converting all the semiconductor material of the isolation region connecting the device regions into dielectric material, such that the device regions are electrically isolated from each other.
1 more element
Dependencies are inferred from the claim text.