Dynamic virtual software pipelining on a network on chip

A network on chip (‘NOC’) for dynamic virtual software pipelining, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC further comprising:

• a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage assigned to a thread of execution on an IP block;
• and
• each stage executing on a thread of execution on an IP block, including a first stage executing on an IP block, producing output data and sending by the first stage the produced output data to a second stage, the output data including control information for the next stage and payload data;
• and
• the second stage consuming the produced output data in dependence upon the control information.

A computer program product for dynamic virtual software pipelining on a network on chip (‘NOC’) and software pipelines, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the computer program product disposed in a computer readable medium, the computer program product comprising computer program instructions capable of:

• segmenting a computer software application into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, including assigning each stage to a thread of execution on an IP block;
• and
• executing each stage on a thread of execution on an IP block, including:
• executing a first stage, producing output data, the output data including control information for the next stage and payload data;
• sending by the first stage the produced output data to a second stage;
• and
• consuming the produced output data by the second stage in dependence upon the control information.