Precise handling of exceptions during program code conversion

A method of precisely handling exceptions with program code conversion from subject code to target code, the method comprising:

• translating the subject code executable by a subject processor into target code executable by a target processor, comprising:
• identifying a fault-vulnerable instruction in the subject code;
• generating one or more counterpart target code instructions as counterparts to the fault-vulnerable subject instruction;
• and
• storing a recovery information associated with the or each counterpart target instruction;
• and
• executing the target code on the target processor, comprising:
• when an exception occurs in relation to a particular one of the counterpart target instructions, locating the recovery information associated with the particular counterpart target instruction;
• executing a recovery routine to rectify a precise subject state representing the subject processor, according to the located recovery information;
• and
• invoking an exception handler to handle the exception with respect to the rectified precise subject state.

A method of precise handling of exceptions with program code conversion from subject code to target code, comprising:

• generating target code including at least one counterpart target instruction which corresponds to a potentially faulting subject instruction in the subject code, and storing recovery information associated with the at least one counterpart target instruction;
• upon receiving an interrupt, continuing execution of target code instructions until encountering the at least one counterpart target instruction;
• upon reaching the counterpart target instruction, recovering a precise subject state using the associated recovery information;
• and
• precisely handling the interrupt using the recovered precise subject state.

A method of precisely handling exceptions with dynamic binary translation from subject code to target code, comprising:

• generating a sequence of target code instructions from a sequence of subject code instructions;
• executing the sequence of target code instructions and, when an exception occurs, rolling forwards along the sequence of target code instructions until encountering a target code instruction where a precise subject state is achievable;
• and
• deferring handling of the exception until the precise subject state is achievable.

A translator apparatus arranged to perform program code conversion from subject code to target code, comprising:

• a translator unit having a decoding unit to decode subject code which is executable by a subject processor according to a subject instruction set architecture, and identify a fault-vulnerable instruction which is potentially faulting in the subject instruction set architecture, and a target code generating unit to generate target code from the subject code, including generating one or more counterpart target instructions from the identified fault-vulnerable subject instruction, and storing recovery information associated with each of the counterpart target instructions;
• a target processor to execute the target code according to a target instruction set architecture;
• a recovery handler unit to retrieve the recovery information associated with a respective one of the one or more counterpart target instructions and recover a precise subject state using the recovery information, when executing the respective one of the counterpart target instructions in the target processor indicates a fault;
• and
• an exception handling unit to precisely handle the fault using the precise subject state.

A translator apparatus arranged to perform program code conversion from subject code to target code, comprising:

• a translator unit to generate target code including at least one counterpart target instruction which corresponds to a potentially faulting subject instruction in the subject code, and to store recovery information associated with the at least one counterpart target instruction;
• a target processor to execute the target code such that, upon receiving an interrupt, execution of target code instructions continues until the at least one counterpart target instruction is encountered;
• a recovery handler to recover a precise subject state using the associated recovery information, when the at least one counterpart target instruction is encountered by the target processor;
• and
• a translated subject exception handler to handle the interrupt using the recovered precise subject state.

A translator apparatus arranged to perform program code conversion from subject code to target code, comprising:

• a translator unit to generate a sequence of target code instructions from a sequence of subject code instructions;
• a target processor to execute the sequence of target code instructions and, when an exception occurs, roll forwards along the sequence of target code instructions until encountering a target code instruction where a precise subject state is achievable;
• and
• an exception handler to handle the exception when the precise subject state is achievable.

A computer-readable medium having recorded thereon instructions implementable by a computer to perform a method of handling precise exceptions under program code conversion from subject code to target code, comprising:

• decoding subject code executable by a subject processor according to a subject instruction set architecture, and identifying a fault-vulnerable instruction which is potentially faulting in the subject instruction set architecture;
• generating target code from the subject code, including generating one or more counterpart target instructions from the identified fault-vulnerable subject instruction, and storing recovery information associated with the or each of the counterpart target instructions;
• executing the target code on a target processor according to a target instruction set architecture;
• and
• when executing the or one of the counterpart target instructions indicates a fault, then performing the steps of:
• retrieving the recovery information associated with the counterpart target instruction;
• recovering a precise subject state which accurately represents the subject processor at the fault, using the recovery information;
• and
• precisely handling the fault using the precise subject state.

A computer-readable medium having recorded thereon instructions implementable by a computer to perform a method of precisely handling exceptions under program code conversion from subject code to target code, the method comprising:

• translating the subject code executable by a subject processor into target code executable by a target processor, comprising:
• identifying a fault-vulnerable instruction in the subject code;
• generating one or more counterpart target code instructions as counterparts to the fault-vulnerable subject instruction;
• storing a recovery information associated with each of the counterpart target instructions(s);
• and
• executing the target code on the target processor, comprising:
• when an exception occurs in relation to a particular one of the counterpart target instructions, locating the recovery information associated with the particular counterpart target instruction;
• executing a recovery routine to rectify a precise subject state representing the subject processor, according to the located recovery information;
• and
• invoking an exception handler to handle the exception with respect to the rectified precise subject state.

A computer-readable medium having recorded thereon instructions implementable by a computer to perform a method of precise handling of exceptions under program code conversion from subject code to target code, comprising:

• generating target code including at least one counterpart target instruction which corresponds to a potentially faulting subject instruction in the subject code, and storing recovery information associated with the at least one counterpart target instruction;
• upon receiving an interrupt, continuing execution of target code instructions until encountering the at least one counterpart target instruction;
• upon reaching the counterpart target instruction, recovering a precise subject state using the associated recovery information;
• and
• precisely handling the interrupt using the recovered precise subject state.