Hardware accelerator

An apparatus, comprising:

• an integrated circuit (IC) comprising:
• a first register configured to receive and hold a first operand;
• a second register configured to receive and hold a second operand;
• a third register and a fourth register;
• an adder/subtractor;
• a shifter unit;
• and
• control circuitry configured to set a mode of the shifter unit wherein the mode corresponds to one of a left shift and a right shift,
• the adder/subtractor configured to add the first operand from the first register, the second operand from the second register and a carry input bit from the shifter unit to generate a sum and a carry out bit;
• the adder/subtractor further configured to load the sum into the third register and to load the carry out bit into the most significant bit position of the third register to generate a third operand;
• the shifter unit configured to perform a single bit shift on the third operand to produce a shifted operand wherein a right shift corresponds to dividing the third operand by two;
• the IC configured to load the shifted operand into the fourth register and to load a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand;
• and
• the IC configured to generate a greatest common divisor (GCD) of the first and second operands using the fourth operand, the IC further configured to generate a public key, based on, at least in part, the GCD.

An article comprising a storage medium having stored thereon instructions that when executed by a machine result in the following:

• adding, by an adder/subtractor, a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit;
• loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand;
• performing a single bit shift on the third operand by a shifter unit to produce a shifted operand wherein a mode of the shifter unit is set by control circuitry, the mode corresponding to one of a left shift and a right shift and a right shift corresponds to dividing the third operand by two;
• loading the shifted operand into the fourth register;
• loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand;
• generating a greatest common divisor (GCD) of the first and second operands using the fourth operand;
• and
• generating a public key, based on, at least in part, the GCD.

A system comprising:

• a switch fabric operatively connected to a plurality of line cards;
• and
• an integrated circuit (IC) comprising:
• a first register configured to receive and hold a first operand;
• a second register configured to receive and hold a second operand;
• a third register and a fourth register;
• an adder/subtractor;
• a shifter unit;
• and
• control circuitry configured to set a mode of the shifter unit wherein the mode corresponds to one of a left shift and a right shift,
• the adder/subtractor configured to add the first operand from the first register, the second operand from the second register and a carry input bit from the shifter unit to generate a sum and a carry out bit;
• the adder/subtractor further configured to load the sum into the third register and to load the carry out bit into the most significant bit position of the third register to generate a third operand;
• the shifter unit configured to perform a single bit shift on the third operand unit to produce a shifted operand wherein a right shift corresponds to dividing the third operand by two;
• the IC configured to load the shifted operand into the fourth register and to load a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand;
• and
• the IC further configured to generate a greatest common divisor (GCD) of the first and second operands using the fourth operand, the IC further configured to generate a public key, based on, at least in part, the GCD.