Voltage island performance/leakage screen monitor for IP characterization

A method of characterizing performance of a chip having a voltage island and at least one performance screen ring oscillator in a region of the chip not associated with the voltage island, the method comprising:

• generating performance measurements of the voltage island with only the voltage island under power using a plurality of on-chip performance monitors on the voltage island;
• generating performance measurements of the performance screen ring oscillator with only the voltage island under power;
• comparing performance measurements of the performance screen ring oscillator to the performance measurements of the on-chip performance monitors to determine a systematic offset due to the voltage island;
• and
• adjusting performance models for the chip using the systematic offset due to the voltage island,
• wherein the performance models include timing models, leakage models, or dynamic power models, and the on-chip performance monitors are respectively located at corners of the voltage island and at a center of the voltage island to account for across chip variation on the voltage island when determining the systematic offset.