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US 8,020,136 B2Granted
Device and method for high-level synthesis
AssigneePanasonic Corporation
InventorsDai Hattori, Keiichi Kurokawa
Life of this patent
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Abstract
A high-level synthesis unit creates a first register transfer level circuit from an operation level description. A circuit creating unit creates a second register transfer level circuit based on circuit information for creating an additional circuit to be added to the first register transfer level circuit. A circuit connecting unit connects the first register transfer level circuit with the second register transfer level circuit, based on connecting information describing a connecting relation between a signal in the first register transfer level circuit and a signal in the second register transfer level circuit.
Claims14
A high-level synthesis device comprising
- a high-level synthesis unit that creates a first register transfer level circuit from an operation level description;
- a circuit creating unit that creates a second register transfer level circuit based on circuit information for creating an additional circuit to be added to the first register transfer level circuit;
- and
- a circuit connecting unit that connects the first register transfer level circuit with the second register transfer lever circuit, based on connecting information describing a connecting relation between a signal in the first register transfer level circuit and a signal in the second register transfer level circuit,
- wherein the high-level synthesis unit calculates a delay amount of a delay circuit depending on a scheduling result of high-level synthesis, and
- wherein the circuit creating unit creates the delay circuit in the second register transfer level circuit using the delay amount.
3 more elements
A high-level synthesis device comprising
- a high-level synthesis unit that creates a first register transfer level circuit from an operation level description;
- and
- a circuit connecting unit that connects the first register transfer level circuit with a second register transfer level circuit, based on connecting information describing a connecting relation between a signal in the first register transfer level circuit and a signal in the second register transfer level circuit that is different from the first register transfer level circuit,
- wherein the high-level synthesis unit calculates a bit width of signal wiring for the connection between the first register transfer level circuit and the second register transfer level circuit depending on a scheduling result of high-level synthesis, and
- wherein the circuit connecting unit connects the first register transfer level circuit and the second register transfer level circuit by the signal wiring with said bit width.
2 more elements
A method for high-level synthesis performed by a high-level synthesis device, said method comprising the steps of:
- creating a first register transfer level circuit from an operation level description;
- determining whether the first register transfer level circuit satisfies prescribed required performance;
- receiving input of circuit information for creating an additional circuit to be added to the first register transfer level circuit to satisfy the required performance and connecting information describing a connecting relation between signals in the first register transfer level circuit including the additional circuit, in a case where it is determined that the first register transfer level circuit does not satisfy the required performance;
- determining whether the first register transfer level circuit including the additional circuit satisfies the required performance, by referring to the first register transfer level circuit and the circuit information;
- creating a second register transfer level circuit based on the circuit information, in a case where it is determined that the first register transfer level circuit including the additional circuit satisfies the required performance;
- and
- creating a target register transfer level circuit by connecting the first register transfer level circuit with the second register transfer level circuit, based on the connecting information,
- wherein a delay amount of a delay circuit is calculated depending on a scheduling result of high-level synthesis,
- the delay circuit in the second register transfer level circuit is created using the delay amount,
- a bit width of signal wiring for the connection between the first register transfer level circuit and the second register transfer level circuit is calculated depending on the scheduling result of high-level synthesis, and
- the first register transfer level circuit and the second register transfer level circuit are connected by the signal wiring with said bit width.
8 more elements
Dependencies are inferred from the claim text.