Method and apparatus for parallel processing of semiconductor chip designs
AssigneeInternational Business Machines Corporation
InventorsMichael W. Dotson, Anthony DeGroff Drumm, Dazhuang J. Ma, Ruchir Puri, Louise H. Trevillyan
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Abstract
In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.
Claims14
A method for processing a semiconductor chip design, comprising:
- flattening a netlist corresponding to the semiconductor chip design to produce a flattened netlist, wherein the flattened netlist comprises a plurality of logic elements and a plurality of interconnects;
- constructing an initial placement of the plurality of logic elements and the plurality of interconnects on a silicon substrate;
- performing logic clustering on the plurality of logic elements to generate one or more clusters, wherein the logic clustering is performed subsequently to the constructing;
- and
- partitioning the semiconductor chip design in accordance with the one or more clusters to form at least two partitions wherein the partitioning is performed in accordance with a slicing-based greedy algorithm that performs steps comprising:
- discretizing a placement image of the semiconductor chip design into a plurality of grids;
- iteratively bisecting the placement image in a biggest region at a time of the bisecting until a predefined number of partitions is obtained,
- wherein at least one of:
- the flattening, the constructing, the performing logic clustering, or the partitioning is performed using a processor.
Computing device containing an executable program for processing a semiconductor chip design, where the program performs the steps of:
- flattening a netlist corresponding to the semiconductor chip design to produce a flattened netlist, wherein the flattened netlist comprises a plurality of logic elements and a plurality of interconnects;
- constructing an initial placement of the plurality of logic elements and the plurality of interconnects on a silicon substrate;
- performing logic clustering on the plurality of logic elements to generate one or more clusters, wherein the logic clustering is performed subsequently to the constructing;
- and
- partitioning the semiconductor chip design in accordance with the one or more clusters to form at least two partitions wherein the partitioning is performed in accordance with a slicing-based greedy algorithm that performs steps comprising:
- discretizing a placement image of the semiconductor chip design into a plurality of grids;
- iteratively bisecting the placement image in a biggest region at a time of the bisecting until a predefined number of partitions is obtained.
Apparatus for processing a semiconductor chip design, comprising:
- means for flattening a netlist corresponding to the semiconductor chip design to produce a flattened netlist, wherein the flattened netlist comprises a plurality of logic elements and a plurality of interconnects;
- means for constructing an initial placement of the plurality of logic elements and the plurality of interconnects on a silicon substrate;
- means for performing logic clustering on the plurality of logic elements to generate one or more clusters, wherein the logic clustering is performed subsequently to the constructing;
- and
- means for partitioning the semiconductor chip design in accordance with the one or more clusters to form at least two partitions wherein the partitioning is performed in accordance with a slicing-based greedy algorithm that performs steps comprising:
- discretizing a placement image of the semiconductor chip design into a plurality of grids;
- iteratively bisecting the placement image in a biggest region at a time of the bisecting until a predefined number of partitions is obtained.
Dependencies are inferred from the claim text.