Clock frequency exploration for circuit designs having multiple clock domains

A method of circuit design comprising:

• receiving clock frequency constraints for a plurality of clock domains of a circuit design, wherein the clock frequency constraints specify a linear programming problem defining inter-dependencies among clock frequencies of the plurality of clock domains;
• determining, by a computer, a solution for the linear programming problem, wherein the solution indicates a feasibility result of the circuit design according to whether a frequency exists for each of the plurality of clock domains that does not violate any of the clock frequency constraints;
• outputting an indication of feasibility of the circuit design;
• in response to the feasibility result indicating that the circuit design is not feasible, performing steps including:
• selecting one of the plurality of clock domains based on respective numbers of timing violations of the plurality of clock domains;
• modifying the clock frequency constraint of the one clock domain;
• and
• determining a feasibility result according to the clock frequency constraints, inclusive of the modified clock frequency constraint;
• responsive to the feasibility result indicating that the circuit design is feasible, determining a clock frequency assignment specifying a clock frequency for each of the plurality of clock domains;
• performing a timing check on the circuit design;
• and
• responsive to determining that the circuit design does not meet at least one timing constraint, generating a new clock frequency constraint according to a result from the timing check.

A computer program product comprising:

• a non-transitory computer-usable medium comprising computer-usable program code that implements a method of circuit design, the computer-usable medium comprising:
• computer-usable program code that receives clock frequency constraints defining relationships between clock frequencies of a plurality of clock domains of a circuit design specified within a high-level modeling system;
• computer-usable program code that receives a cost function that is dependent upon the clock frequencies of the plurality of clock domains;
• computer-usable program code that determines a feasibility result according to the clock frequency constraints and the cost function, wherein the feasibility result indicates whether a clock frequency assignment exists that specifies a clock frequency for each of the plurality of clock domains that does not violate any clock frequency constraint;
• computer-usable program code that outputs the feasibility result;
• computer-usable program code that, responsive to the feasibility result indicating that the circuit design is not feasible, performing steps including:
• selects one of the plurality of clock domains based on respective numbers of timing violations of the plurality of clock domains;
• modifies the clock frequency constraint of the one clock domain;
• and
• determines a feasibility result according to the clock frequency constraints, inclusive of the modified clock frequency constraint, and the cost function;
• computer-usable program code that, responsive to the feasibility result indicating that the circuit design is feasible, determines a clock frequency assignment specifying a clock frequency for each of the plurality of clock domains;
• computer-usable program code that performs a timing check on the circuit design;
• and
• computer-usable program code that, responsive to determining that the circuit design does not meet at least one timing constraint, generates a new clock frequency constraint according to a result from the timing check.