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US 8,020,122 B2Granted
Circuit splitting in analysis of circuits at transistor level
AssigneeThe Regents of the University of California
InventorsChung-Kuan Cheng, Zhengyong Zhu, Rui Shi
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Abstract
Operating splitting methods for splitting a circuit into two sub circuits and analyzing the two sub circuits with improved computation efficiency and processing speed.
Claims25
A method for analyzing an integrated circuit, comprising:
- representing the integrated circuit with an undirected graph;
- from one or more nodes connected to GND or VDD in the graph, conducting a search, using a processor, for nodes in the undirected graph;
- dividing edges of nodes from the search to form exactly two subgraphs that respectively represent two sub circuits of the integrated circuit;
- modifying the divided two subgraphs to ensure each node of each subgraph to have a DC path to GND or VDD;
- and
- analyzing, using the processor, the two subgraphs.
3 more elements
An article comprising at least one non-transitory machine-readable medium that stores machine-executable instructions, the instructions causing a machine to:
- represent the integrated circuit with an undirected graph;
- from one or more nodes connected to GND or VDD in the graph, conduct a search for nodes in the undirected graph;
- divide edges of nodes from the search to form exactly two subgraphs that respectively represent two sub circuits of the integrated circuit;
- modify the divided two subgraphs to ensure each node of each subgraph to have a DC path to GND or VDD;
- and
- analyze the two subgraphs.
3 more elements
An article comprising at least one non-transitory machine-readable medium that stores machine-executable instructions, the instructions causing processor electronics to perform operations comprising:
- representing an integrated circuit as an undirected graph;
- conducting, from one or more nodes connected to GND or VDD in the graph, a search to identify nodes in the undirected graph;
- dividing edges of nodes identified during the search to form exactly two subgraphs that respectively represent two sub circuits of the integrated circuit, wherein the two sub circuits represent independent circuit paths;
- modifying the divided two subgraphs to ensure each node of each subgraph has a DC path to GND or VDD, wherein an edge assigned to one of the two subgraphs can be reassigned to the other subgraph to provide a DC path for the edge;
- and
- analyzing the two subgraphs.
3 more elements
Dependencies are inferred from the claim text.