Layout quality gauge for integrated circuit design

A method for layout design, the method comprising steps of:

• using a processor for:
• receiving a layout for design of an integrated circuit chip;
• obtaining a description of process variability specifying process conditions;
• obtaining mask shapes designed for the layout, subject to the specified process conditions to compute gates over the layout for each process point in a process window;
• transmitting the mask shapes to a litho simulator for generating wafer shapes;
• receiving the wafer shapes from the litho simulator;
• calculating electrically equivalent gate lengths for the wafer shapes;
• analyzing the gate lengths for conformance to threshold values, wherein the threshold values represent acceptable values of electrically equivalent gate lengths;
• placing markers on the layout at those locations where the gate length violates the threshold value;
• and
• generating a histogram of the gate lengths for comparing the layout to other layouts for layout quality by checking conformity to specified variations of electrically equivalent gate lengths.

A computer program product tangibly embodied on a non-transitory computer readable medium and storing code that, when executed, causes a computer to perform a method comprising:

• receive a layout for design of an integrated circuit chip;
• obtaining a description of process variability specifying process conditions;
• obtain mask shapes designed for the layout, subject to the specified process conditions to compute gates over the layout for each process point in a process window;
• transmit the mask shapes to a litho simulator for generating wafer shapes;
• receive the generated wafer shapes from the litho simulator;
• calculate electrically equivalent gate lengths for the wafer shapes;
• analyze the gate lengths to check conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate length;
• place markers on the layout at those locations where the gate length violates the threshold value;
• and
• generate a histogram of gate lengths for comparing the layout to other layouts for layout quality by checking conformity to specified variation of electrically equivalent gate lengths.