Memory system and command handling method
AssigneeSamsung Electronics Co., Ltd.
InventorJung-Bae Lee
Life of this patent
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Abstract
A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.
Claims20
In a memory system comprising a memory controller and a memory, a method comprising:
- communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory;
- decoding the command and executing an EDC operation related to the EDC data in parallel, wherein decoding the command comprises receiving a command packet in a packet receiver and in response generating an internal command, internal EDC data, and an internal address;
- and
- if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else
- immediately executing an operation indicated by the command without regard to completion of the EDC operation,
- wherein executing the EDC operation comprises:
- applying the internal EDC data, the internal command, and the internal address to an error detector;
- generating an error signal in the error detector in relation to the internal command, internal address, and the internal EDC data;
- and
- applying the error signal to a write enable signal transfer block.
The method of 1 wherein the EDC operation implements a cyclic redundancy checker (CRC) and the EDC data comprises CRC data.
In a memory system comprising a memory controller and a memory, a method comprising:
- communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, wherein the command communicated from the memory controller to the memory comprises a first command packet including control data, address data, and first EDC data associated with at least one of the control data and address data, and a second command packet including write data and second EDC data associated with the write data,
- decoding the command and executing an EDC operation in parallel, wherein the EDC operation is related to at least one of the first EDC data and the second EDC data, and decoding the command signal comprises receiving the first command packet in a packet receiver and in response generating an internal command, an internal address, first internal EDC data, and a first packet indicating signal;
- and
- if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else
- immediately executing an operation indicated by the command without regard to completion of the EDC operation,
- wherein executing the EDC operation comprises:
- applying the first internal EDC data, the internal command, the first packet indicating signal, and the internal address to an error detector;
- generating a first error signal in the error detector in relation to the internal command, the first EDC data, internal address, and the first packet indicating signal;
- and
- applying the first error signal to a write signal transfer block.
Dependencies are inferred from the claim text.