Method of arranging data in a multi-level cell memory device

#The present invention relates to Multi-Level Cell Flash memory devices. More particularly, the invention relates to the field of Error Correction in a Multi-Level Cell Flash memory device.

#Flash memory devices have been known for many years. Within all Flash memory devices, NAND-type memories differ from other type memories (e.g. NOR), among other specific characteristics, by the fact that a number of information bits written to the memory may be read back in a “flipped” manner, i.e. different from way these bits have been originally written to the memory.

#In order to overcome this phenomenon of obtaining “flipped” bits and to make NAND-type memories usable by real applications, it is a common technique to utilize ECC (Error Correction Code) algorithms in conjunction with these NAND-type memories. An ECC algorithm is typically employed by Flash memories as follows: Before writing data to the memory, an ECC algorithm is applied to this data in order to compute additional (redundant) information bits. These redundant bits are often called “parity bits” or “parity” and are later used for error detection and correction. The combination of the original data and the parity is called a “codeword” The entire codeword (i.e the original data and the parity) is recorded to the Flash memory device,. It should be noted that the actual size of the NAND Flash memory device is designed to accommodate the original data as well as the parity. When the data is retrieved from the memory, the entire codeword is read and an ECC algorithm is applied to the data and the parity in order to detect and correct possible “bit flips” (i.e. errors).

#For a better understanding of the invention with regard to the embodiment thereof, reference is made to the accompanying drawings, in which like numerals designate corresponding sections or elements throughout, and in which:

#FIG. 1 is a block diagram of a system of the present invention;

#FIG. 2A is an exemplary illustrative, non-limiting diagram of logical pages associated, by a host computer, to data bits of a 4-bit per cell memory device having a page of N cells; and

#The present invention is of a method of interleaving input data between different bit-pages of a physical page of an MLC memory device when used in conjunction with specific ECC algorithms in order to minimize processing time and power consumption of to prior art techniques.

#Let us consider an ECC scheme, in which, in order to detect and correct “flipped” bits a search of all the data bits is required As an example for such a scheme, BCH decoding may be considered.

#When implementing a BCH decoder for relatively large number of bit errors (generally, larger than 4), it is common to detect the data bits to be corrected using a “Chein Search”. See for example, W. Wesley Peterson, E. J. Weldon, Jr., “Error-Correcting Codes”, Second Edition, The Massachusetts Institute of Technology, 1972, which is incorporated by reference for all purposes as if fully set forth herein. The “Chein Search” does a bit scan of the codeword, checking whether or not a specific bit is an erroneous bit and, therefore, shall be flipped. But the total number of the erroneous bits in a codeword is limited by the codeword structure and is generally computed by the decoding algorithm stages, which precede “Chein Search”. Therefore, the exact number of erroneous bits to be corrected can be determined by the ECC algorithm prior to the bit scanning of the code word (using “Chein Search”).