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US 8,020,040 B2Granted
Information processing apparatus for handling errors
AssigneeFujitsu Limited
InventorNoriyoshi Tanaka
Life of this patent
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Abstract
In the event of occurrence of an error in a memory in an information processor, a first processor that is one of a number of processors executes an error handler program stored in a first memory that is one of a number of memories. If the first processor fails in correctly operating the error handler program, a second processor different from the first processor executes an error handler program stored in a second memory different from the first memory.
Claims4
An information processing apparatus comprising:
- a plurality of processors comprising a first processor and a second processor;
- a plurality of memories comprising a first memory and a second memory;
- and
- a plurality of devices,
- at least two error handler program retaining sections which are provided at least to said first memory and said second memory and which retain an error handler program,
- if an error occurs in one of said memories,
- said first processor executing the error handler program stored in said first memory,
- if said first processor has failed to normally complete the error handler program,
- said second processor executing the error handler program stored in said second memory,
- if a second error occurs at one of said devices,
- said first processor sequentially accessing one or more non-extracted devices from which information has not been extracted among said devices in a first scanning order to extract information from each of the non-extracted devices, and the second processor sequentially accessing the non-extracted devices in a second scanning order reverse to the first scanning order to extract information from the non-extracted devices.
8 more elements
An information processor comprising:
- a plurality of processors including a first processor and a second processor;
- a memory;
- and
- a plurality of devices,
- if an error occurs while a process is being performed on one of the devices,
- said first processor sequentially accessing one or more non-extracted devices from which information has not been extracted among said devices in a first scanning order to extract information from each of the non-extracted devices, and the second processor sequentially accessing the non-extracted devices in a second scanning order reverse to the first scanning order to extract information from the non-extracted devices.
3 more elements
Dependencies are inferred from the claim text.