Timing control in a specialized processing block
AssigneeAltera Corporation
InventorMichael D. Hutton
Life of this patent
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Abstract
The tension between fmax and Tco in a specialized processing block of a programmable integrated circuit device can be reduced by providing variable delays on the clock inputs of the pipeline registers within the specialized processing block. This allows the introduction of beneficial skew that allows slower functions to be performed within the specialized processing block rather than outside the block, thereby reducing Tco, without slowing down the clock—i.e., without reducing fmax. This technique may also apply to other specialized blocks such as memory.
Claims15
A specialized block in a programmable integrated circuit device, said specialized block comprising:
- a plurality of function elements arranged in a pipeline with a plurality of pipeline registers;
- a clock conductor providing a clock signal to said pipeline registers;
- a respective programmable delay associated with each respective one of at least one of said pipeline registers;
- and
- a respective selector associated with each said respective pipeline register, each said respective selector having as inputs (a) said clock signal, and (b) said clock signal delayed by said respective programmable delay;
- whereby:
- said respective selector selectably connects one of (a) said clock signal, and (b) said clock signal delayed by said respective programmable delay, to said respective one of said least one of said pipeline registers.
A method of configuring timing of a specialized block in a programmable integrated circuit device, said specialized block including a plurality of function elements arranged in a pipeline with a plurality of pipeline registers, a clock conductor providing a clock signal to said pipeline registers, a respective programmable delay associated with each respective one of at least one of said pipeline registers, and a respective selector associated with each said respective pipeline register, said method comprising:
- configuring said functional elements relative to said registers in accordance with constraints of said timing;
- configuring said clock conductor and each said respective programmable delay as inputs to each said respective selector;
- and
- configuring each said respective selector to select one of (a) said clock signal, and (b) said clock signal delayed by said respective programmable delay, according to said configuring of said functional elements relative to said registers.
A machine-readable data storage medium encoded with machine-executable instructions for configuring timing of a specialized block in a programmable integrated circuit device, said specialized block including a plurality of function elements arranged in a pipeline with a plurality of pipeline registers, a clock conductor providing a clock signal to said pipeline registers, a respective programmable delay associated with each respective one of at least one of said pipeline registers, and a respective selector associated with each said respective pipeline register, said instructions comprising:
- instructions to configure said functional elements relative to said registers in accordance with constraints of said timing;
- instructions to configure said clock conductor and each said respective programmable delay as inputs to each said respective selector;
- and
- instructions to configure each said respective selector to select one of (a) said clock signal, and (b) said clock signal delayed by said respective programmable delay, according to said configuring of said functional elements relative to said registers.
Dependencies are inferred from the claim text.