Delay time control of memory controller
AssigneeFujitsu Limited
InventorNoriyuki Tokuhiro
Life of this patent
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Abstract
A memory control circuit has a write leveling function and controls read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection. For each of the plurality of memories, a first variable delay unit delays, in a write operation, a data strobe signal output to the memory by a first delay time that is set by utilizing the write leveling function and a second variable delay unit delays, in a read operation, a data signal input from the memory by a second delay time that is set based on the first delay time.
Claims16
A memory control circuit having a write leveling function and controlling read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection, the memory control circuit comprising:
- for each of the plurality of memories:
- a first variable delay unit delaying, in a write operation, a data strobe signal output to the memory by a first delay time that is set by utilizing the write leveling function;
- and
- a second variable delay unit delaying, in a read operation, a data signal input from the memory by a second delay time that is set based on the first delay time,
- wherein
- the first variable delay unit is constituted by a digital delay circuit which is made up of a plurality of unit circuits connected in series and which delays the data signal output to the memory by the first delay time by passing the data signal through a predetermined number of the unit circuits;
- and
- the second variable delay unit is constituted by the digital delay circuit which is made up of the plurality of unit circuits connected in series and which delays the data signal input from the memory by the second delay time by passing the data signal through a predetermined number of the unit circuits.
A delay time control device setting a signal delay time in a memory control circuit having a write leveling function and controlling read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection, the delay time control device comprising:
- a first delay time controller setting a first delay time of a data strobe signal, which is output to each memory in a write operation, corresponding to each of the plurality of memories by utilizing the write leveling function;
- and
- a second delay time controller setting, based on the first delay time set by the first delay time controller, a second delay time of a data signal, which is input from each memory in a read operation, corresponding to each of the plurality of memories,
- wherein
- the first delay time controller delays the data signal output to the memory by the first delay time by passing the data signal through a part of a digital delay circuit which is made up of a plurality of unit circuits connected in series;
- and
- the second delay time controller delays the data signal input from the memory by the second delay time by passing the data signal through a part of the digital delay circuit which is made up of the plurality of unit circuits connected in series.
A delay time control method for setting a signal delay time in a memory control circuit having a write leveling function and controlling read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection, the delay time control method comprising:
- setting a first delay time of a data strobe signal, which is output to each memory in a write operation, corresponding to each of the plurality of memories by utilizing the write leveling function;
- and
- setting, based on the first delay time set, a second delay time of a data signal, which is input from each memory in a read operation, corresponding to each of the plurality of memories,
- wherein
- the first delay time setting delays the data signal output to the memory by the first delay time by passing the data signal through a part of a digital delay circuit which is made up of a plurality of unit circuits connected in series;
- and
- the second delay time setting delays the data signal input from the memory by the second delay time by passing the data signal through a part of the digital delay circuit which is made up of the plurality of unit circuits connected in series.
Dependencies are inferred from the claim text.