Memory power controller

A memory power controller, comprising:

• clock synchronization circuitry connected to receive a source clock and a memory time out signal for generating a delayed clock source responsive to the received clock source and for generating a memory enable/disable signal to control operation of an associated memory, the memory enable/disable signal comprising the memory timeout signal synchronized to occur at a predetermined time period with respect to the delayed clock source, the synchronization moves an active edge of the timeout signal away from an active edge of the delay clock source;
• a clock period measurement circuit for determining when a period of the delayed source clock exceeds a predetermined period and generating the memory time out signal indicating that the delayed source clock has a period greater than the predetermined period;
• first pulse generation circuitry for generating a first clock signal responsive to the memory time out signal indicating that memory has been turned on long enough to use;
• second pulse generation circuitry for generating a second clock signal responsive to the delayed source clock;
• a multiplexer having inputs connected to receive the first clock signal and the second clock signal, wherein the multiplexer selects the first clock signal or the second clock signal responsive to a control input;
• and
• a state machine for generating the control input responsive to the delayed source clock and memory enable/disable signal, wherein the state machine generates the control input to select the first clock signal when the period of the delayed source clock is greater than the predetermined value and further wherein the state machine generates the control input to select the second clock signal when the period of the delayed source clock is less than the predetermined value.

A method for providing power control to a memory comprising the steps of:

• determining if a source clock has a period greater than or less than a predetermined value;
• generating each of a first clock signal and a second clock signal responsive to at least one of a source clock and the determination that the source clock has a period greater than a predetermined value;
• selecting the first clock signal responsive to the determination that the source clock has a period greater than the predetermined value;
• selecting the second clock responsive to the determination that the source clock has a period less than the predetermined value;
• generating a memory enable/disable signal to control operation of an associated memory responsive to the source clock and the determination that the source clock has a period greater than the predetermined value;
• and
• synchronizing the memory enable/disable signal to occur a predetermined period with respect to a delayed version of the source clock.