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US 8,019,981 B1Granted
Loop instruction execution using a register identifier
AssigneeAltera Corporation
InventorPaul Metzgen
Life of this patent
Estimating the term…
Abstract
Methods and apparatus are provided for performing loop execution. Modifier registers are used to hold loop counter values. Modifier register information and program memory address information are included in the loop instruction. When a processor executes a loop instruction, it decodes the instruction, identifies the modifier register, and accesses the register value to determine if the processor will jump back based on the memory address information. The loop execution can incur no clock cycle penalties.
Claims30
A method comprising:
- receiving, within a loop instruction, an address associated with a first nested loop, wherein the first nested loop includes the loop instruction;
- receiving, within the loop instruction, a register identifier identifying a first register of a processor;
- determining whether a value stored in the first register is greater than zero, wherein said value is associated with a number of times the first nested loop has been executed;
- and
- decrementing the value and performing an operation in parallel with the decrementing in response to determining that the value stored in the first register is greater than zero.
2 more elements
A processor comprising:
- an execution circuit operable to execute a loop instruction within a first nested loop;
- and
- a first register operable to be identified by a register identifier within the loop instruction,
- wherein the loop instruction includes a program memory address associated with the first nested loop,
- wherein the execution circuit is operable to determine whether a value stored in the first register is greater than zero, wherein the value is associated with a number of times the first nested loop has been executed, and
- wherein, in response to determining that the value stored in the first register is greater than zero, the execution circuit is operable to decrement the value and perform an operation in parallel.
3 more elements
A system comprising:
- first means for modifying;
- and
- means for receiving, within a loop instruction in a first nested loop, a program memory address associated with the first nested loop and receiving, within the loop instruction, a register identifier identifying the first means for modifying,
- wherein the means for receiving determines whether a value stored in the first means for modifying is greater than zero, wherein the value is associated with a number of times the first nested loop has been executed, and
- wherein the means for receiving decrements the value and performs an operation in parallel in response to determining that the value stored in the first means for modifying is greater than zero.
2 more elements
Dependencies are inferred from the claim text.