Efficient implementation of branch intensive algorithms in VLIW and superscalar processors

A method of efficiently processing a branch intensive algorithm comprising:

• configuring a lookup table with a truth table for an identified branching portion of the branch intensive algorithm;
• processing conditional statements of the identified branching portion in separate execution units of a processor;
• providing the outcomes of the conditional statement processing to the lookup table;
• processing possible results of the identified branching portion in separate pipelines of the processor;
• generating a selection signal from the lookup table based upon the configured truth table and outcomes of the conditional statement processing;
• providing the outputs of the results processing to guarded result registers;
• writing data in the guarded result register enabled by the selection signal;
• and
• configuring the lookup table with an appropriate truth table for the next identified branching portion;
• wherein the branch intensive algorithm is selected from the group consisting of JPEG 2000, VC-3, VC-2, MC-FRC, De-Interlacing, Noise Reduction, and Detail Enhancement.

An apparatus for efficiently implementing an audio, video, or graphic processing algorithm comprising:

• a VLIW processor comprising:
• a plurality of ALUs;
• a plurality of result registers, each result register being responsive to outputs of the plurality of ALUs;
• wherein the plurality of result registers each have a guard input;
• wherein the guard inputs of the plurality of result registers are responsive to a selection signal enabling the plurality of ALUs to write contents at a proper result register;
• a register file responsive to outputs of the plurality of ALUs to store outputs from the plurality of ALUs;
• a lookup table dynamically programmed with logic to implement a plurality of upcoming logic equations, the lookup table being responsive to the register file;
• wherein the lookup table outputs the selection signals based upon outputs from the plurality of ALUs and the programmed logic for implementing the plurality of upcoming logic equations;
• wherein the processing algorithm is selected from the group consisting of JPEG 2000, VC-3, VC-2, MC-FRC, De-Interlacing, Noise Reduction, and Detail Enhancement.