Generating predicate values during vector processing
AssigneeApple Inc.
InventorsJeffry E. Gonion, Keith E. Diefendorff
Life of this patent
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Abstract
A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more predicate values corresponding to any detected conflict between the memory addresses, where a given predicate value indicates elements in at least the portion of the vector that can be processed in parallel. Next, the processor executes the instructions for detecting the conflict between the memory addresses and generating the one or more predicate values.
Claims30
A method for performing parallel operations in a computer system when one or more memory hazards may be present, comprising:
- at runtime, receiving instructions for detecting conflicts between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more predicate values corresponding to any detected conflict between the memory addresses, wherein a given predicate value indicates elements in at least the portion of the vectors that can be processed in parallel, wherein the conflicts between the memory addresses are data-dependent and therefore cannot be detected until after the memory addresses have been resolved at runtime, and wherein the instructions are inserted in program code prior to runtime;
- wherein while executing the program code, executing the instructions causes a processor to detect the conflict between the memory addresses and generate the one or more predicate values.
A compiler configured to generate a set of instructions based on a feature set of a processor, wherein the processor is configured to:
- at runtime, receive instructions for detecting conflicts between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more predicate values corresponding to any detected conflict between the memory addresses, wherein a given predicate value indicates elements in at least the portion of the vectors that can be processed in parallel, wherein the conflicts between the memory addresses are data-dependent and therefore cannot be detected until after the memory addresses have been resolved at runtime, and wherein the compiler inserts the instructions in program code prior to runtime;
- and
- execute the instructions while executing the program code, wherein executing the instructions causes the processor to detect the conflict between the memory addresses and generate the one or more predicate values.
A computer system configured to execute a set of instructions to avoid one or more memory hazards while performing parallel operations, comprising:
- a processor;
- a memory;
- an instruction fetch unit within the processor configured to, at runtime, fetch instructions for detecting conflicts between memory addresses in vectors when operations are performed in parallel using at least a portion of the vectors, and generating one or more predicate values corresponding to any detected conflict between the memory addresses, wherein a given predicate value indicates elements in at least the portion of the vectors that can be processed in parallel, wherein the conflicts between the memory addresses are data-dependent and therefore cannot be detected until after the memory addresses have been resolved at runtime, and wherein the instructions are inserted in program code prior to runtime;
- and
- an execution unit within the processor configured to execute the instructions while executing the program code, wherein executing the instructions causes the processor to detect the conflict between the memory addresses and generate the one or more predicate values.
Dependencies are inferred from the claim text.