Pipeline processor with write control and validity flags for controlling write-back of execution result data stored in pipeline buffer register

A pipeline processor including a first stage to read data from a general purpose register unit, a second stage to execute instruction, and a third stage to write back the data into the general purpose register unit, the pipeline processor comprising:

• a first pipeline register provided between the second stage and the third stage, the first pipeline register including a first area to store a data validity flag indicating validity of data retained by the first pipeline register and a second area to store a WRITE control flag to control writing the retained data into the general purpose register unit, the data retained in the first pipeline register being allowed to be written back into the general purpose register when the WRITE control flag indicates “valid”;
• a second pipeline register provided between the first stage and the second stage;
• one of a first arithmetic logic unit and a first memory to execute instruction in the second stage, the one of the first arithmetic logic unit and the first memory being supplied with data from the second pipeline register and supplying output data to the first pipeline register;
• a bypass circuit to selectively supply the data retained in the first pipeline register to the second pipeline register when the data validity flag indicates “valid,” wherein
• the data validity flag and the WRITE control flag become “valid” when each of preceding and subsequent instructions for rewriting the general purpose register reaches the third stage,
• the WRITE control flag becomes “invalid” when the data retained in the first pipeline register is written into the general purpose register unit, and
• the data validity flag becomes “invalid” when a subsequent instruction is provided to the third stage that invalidates the data retained in the first pipeline register, and wherein
• the first pipeline register continues to retain the retained data even after the writing of the retained data into the general purpose register unit ends, and
• the first pipeline register provides the retained data to the second pipeline register through the bypass circuit at the time of executing a subsequent instruction having data dependency on a preceding instruction.