Information processing apparatus and method of controlling register

An information processing apparatus including a plurality of register windows including combinations of registers in order of in registers, local registers, and out registers, for executing Simultaneous MultiThreading, the information processing apparatus comprising:

• a plurality of register windows each includes a master register and a work register provided for each of plural threads;
• a data transfer bus shared between the threads and configured to transfer data from the master register to the work register;
• an instruction analysis unit configured to decode an instruction read from a memory device;
• an instruction issue control unit configured to perform control to issue the decoded instruction to a computation unit configured to execute the decoded instruction;
• an instruction completion control unit configured to obtain an instruction execution result of the computation unit and to perform control for updating the register set on the basis of the execution result;
• and
• a data transfer control unit configured to control data transfer from the master register to the work register, wherein
• the data transfer control unit comprises:
• a flag generation unit configured to receive a work register rewrite request signal output for each of the threads from the instruction completion unit, to generate a flag instructing starting of a LOAD-CWP process of the thread specified by the work register rewrite request signal and to output the flag to a data transfer timing control unit in order to perform a process of rewriting data in a work register for each of the threads;
• a data transfer control counter configured to count cycles for data transfer on the basis of the flag;
• a data transfer timing control unit configured to control data transfer at a prescribed timing on the basis of the flag and cycles of the data transfer;
• and
• an instruction issue inhibition control unit configured to output, on the basis of the cycles for the data transfer, an instruction inhibition signal for inhibiting the instruction during data transfer.