Three-dimensional networking design structure

A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

• a multi-layer silicon stack architecture having one or more processing layers comprised of one or more computing elements;
• one or more networking layers disposed between the processing layers, the network layer comprised of one or more networking elements, the one or more networking elements including one or more links to an external network,
• wherein each computing element comprises a plurality of network connections to adjacently disposed networking elements,
• each computing element is connected to a plurality of networking elements, each networking element is connected to a plurality of computing elements,
• the computing elements and the networking elements are connected by one or more serial or parallel connections,
• the computing elements include a processor chip,
• the networking elements include a switch chip and an edge switch chip,
• the edge switch chip is connected to two processor chips,
• the networking elements further include a switch chip on a third layer,
• the switch chip on a third layer is connected to four switch chips on a second layer, and
• each networking element may provide network access to up to eight other computing elements through a single hop of the network.

A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

• a multi-layer silicon stack architecture having a first and second processing layer each comprised of one or more computing elements;
• a networking layer disposed between the first and second processing layers, the network layer comprised of one or more networking elements,
• wherein each computing element comprises a plurality of network connections to adjacently disposed networking elements, the one or more networking elements including one or more links to an external network,
• each computing element is connected to a plurality of networking elements, each networking element is connected to a plurality of computing elements,
• the computing elements and the networking elements are connected by one or more serial or parallel connections,
• the computing elements include a processor chip,
• the networking elements include a switch chip and an edge switch chip,
• the edge switch chip is connected to two processor chips,
• the networking elements further include a switch chip on a third layer,
• the switch chip on a third layer is connected to four switch chips on a second layer, and
• each networking element may provide network access to up to eight other computing elements through a single hop of the network.