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US 8,019,969 B2Granted
Self prefetching L3/L4 cache mechanism
AssigneeInternational Business Machines Corporation
InventorDavid A. Luick
Life of this patent
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Abstract
Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data from a cache. A subset of real address bits associated with an effective address may be retrieved relatively quickly from the LLB, thereby allowing access to the cache before the complete address translation is available and reducing cache access latency.
Claims18
A method for retrieving data from memory, comprising:
- receiving an effective address;
- transmitting the effective address to a translation look-aside buffer (TLB) to retrieve a real address associated with the effective address;
- using a first set of effective address bits as an index to a look-aside-look-aside buffer (LLB) to retrieve a first set of real address bits, wherein the LLB is configured to store a subset of address translations contained in the TLB;
- using the first set of real address bits and a second set of effective address bits to access the memory;
- and
- completing memory access using the real address retrieved from the TLB.
3 more elements
A system comprising:
- at least one processor core;
- at least one memory device;
- a buffer;
- and access circuitry configured to:
- receive an effective address from the at least one processor core;
- transmit the effective address to a Translation Look-aside Buffer (TLB) to retrieve a real address associated with the effective address;
- use a first set of effective address bits as an index to the buffer to retrieve a first set of real address bits, wherein the buffer is configured to store a subset of address translations contained in the TLB;
- use the first set of real address bits and a second set of effective address bits to access the memory device;
- and
- complete access to the memory device using the real address retrieved from the TLB.
7 more elements
A processor comprising:
- a cache;
- a translation look-aside buffer (TLB);
- a look-aside-look-aside buffer (LLB);
- and access circuitry configured to:
- receive an effective address;
- transmit the effective address to the (TLB) to retrieve a real address associated with the effective address;
- use a first set of effective address bits as an index to the LLB to retrieve a first set of real address bits, wherein the LLB is configured to store a subset of address translations contained in the TLB;
- use the first set of real address bits and a second set of effective address bits to initiate access to the cache;
- and
- complete cache access using the real address retrieved from the TLB.
7 more elements
Dependencies are inferred from the claim text.