Back to results
US 8,019,968 B2Granted
3-dimensional L2/L3 cache array to hide translation (TLB) delays
AssigneeInternational Business Machines Corporation
InventorDavid A. Luick
Life of this patent
Estimating the term…
Abstract
Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data from a cache. A subset of real address bits associated with an effective address may be retrieved relatively quickly from the LLB, thereby allowing access to the cache before the complete address translation is available and reducing cache access latency.
Claims20
A method for retrieving data from an L2 cache, comprising:
- receiving an effective address of memory to be accessed from a level 2 (L2) cache;
- transmitting the effective address to a translation look-aside buffer (TLB) to retrieve a stored real address associated with the effective address;
- using a first set of effective address bits as an index into a real address array to retrieve trial real address bits;
- using bits of the trial real address to at least initiate access the L2 cache;
- comparing the trial real address bits to bits in the real address retrieved from the TLB;
- if the trial real address bits and real address bits retrieved from the TLB match, completing the access using the trial real address;
- and
- if the trial real address bits and real address bits retrieved from the TLB do not match, completing the access using the real address retrieved from the TLB.
5 more elements
A system comprising:
- at least one processor core;
- at least one L2 cache;
- a real address array;
- a Translation Look-aside Buffer (TLB);
- and
- access circuitry configured to receive an effective address from the at least one processor core, retrieve trial real address bits from the real address array to initiate access to the L2 cache, retrieve a real address associated with the effective address from the TLB, compare the trial real address bits to bits in the real address retrieved from the TLB, if the trial real address bits and real address bits retrieved from the TLB match, complete the access using the trial real address, and if the trial real address bits and real address bits retrieved from the TLB do not match, complete the access using the real address retrieved from the TLB.
3 more elements
A processor comprising:
- at least one L2 cache;
- a real address array;
- a Translation Look-aside Buffer (TLB);
- and
- access circuitry configured to receive an effective address, retrieve trial real address bits from the real address array to initiate access to the L2 cache, retrieve a real address associated with the effective address from the TLB, compare the trial real address bits to bits in the real address retrieved from the TLB, if the trial real address bits and real address bits retrieved from the TLB match, complete the access using the trial real address, and if the trial real address bits and real address bits retrieved from the TLB do not match, complete the access using the real address retrieved from the TLB.
2 more elements
Dependencies are inferred from the claim text.