US 8,019,949 B2Granted

High capacity memory subsystem architecture storing interleaved data for reduced bus speed

AssigneeInternational Business Machines Corporation

InventorsGerald Keith Bartley, John Michael Borkenhagen, Philip Raymond Germann

Life of this patent

Estimating the term…

Loading patent…

Abstract

A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

Claims18

Dependent claims

A memory apparatus for a computer system, comprising:

a memory controller issuing memory access commands, each memory access command accessing an accessible unit of data;
at least one hub communicating with said memory controller over a first communications medium, said first communications medium comprising at least one first point-to-point communications link, each said first point-to-point communications link coupling a respective hub of said at least one hub with one of (a) said memory controller, and (b) a module intermediate said memory controller and the respective hub in a chain of point-to-point communications links, said first communications medium transferring data at a first bus frequency and requiring N cycles to communicate said accessible unit of data, where N is greater than one;
and
a plurality of memory modules arranged in at least one cluster, each said cluster communicating with a respective hub of said at least one hub over a second communications medium, at least a portion of said second communications medium comprising at least one second point-to-point communications link transferring data at a second bus frequency less than said first bus frequency, said at least a portion of said second communications medium requiring M cycles to communicate said accessible unit of data, wherein M is at least one and less than N, each second point-to-point communications link of said at least one second point-to-point communications link coupling a respective hub of said at least one hub with a respective memory module of said plurality of memory modules, each memory module of a respective cluster of said plurality of memory modules storing a respective portion of respective data accessed by each memory access command for accessing data in the respective cluster issued by said memory controller.

1 more element

A computer system, comprising:

at least one processor;
a memory for storing data in addressable storage locations accessed by said at least one processor, said memory comprising:
(a) a memory controller issuing memory access commands, each memory access command accessing an accessible unit of data;
(b) at least one hub communicating with said memory controller over a first communications medium, said first communications medium comprising at least one first point-to-point communications link, each said first point-to-point communications link coupling a respective hub of said at least one hub with one of (a) said memory controller, and (b) a module intermediate said memory controller and the respective hub in a chain of point-to-point communications links, said first communications medium transferring data at a first bus frequency and requiring N cycles to communicate said accessible unit of data, where N is greater than one;
and
(c) a plurality of memory modules arranged in at least one cluster, each said cluster communicating with a respective hub of said at least one hub over a second communications medium, at least a portion of said second communications medium comprising at least one second point-to-point communications link transferring data at a second bus frequency less than said first bus frequency, said at least a portion of said second communications medium requiring M cycles to communicate said accessible unit of data, wherein M is at least one and less than N, each second point-to-point communications link of said at least one second point-to-point communications link coupling a respective hub of said at least one hub with a respective memory module of said plurality of memory modules, each memory module of a respective cluster of said plurality of memory modules storing a respective portion of respective data accessed by each memory access command for accessing data in the respective cluster issued by said memory controller.

3 more elements

Dependencies are inferred from the claim text.