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US 8,019,922 B2Granted
Interruption facility for adjunct processor queues
AssigneeInternational Business Machines Corporation
InventorsCharles W. Gainey, Jr., Klaus Meissner, Damian L. Osisek, Klaus Werner
Life of this patent
Estimating the term…
Abstract
Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.
Claims22
A computer program product for executing a machine instruction in a central processing unit, the computer program product comprising:
- a computer readable storage medium readable by a processor and storing instructions for execution by the processor for performing a method comprising:
- obtaining, by the central processing unit, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
- an opcode field specifying a process adjunct processor queue instruction, the process adjunct processor queue instruction to enable or disable interrupts for a queue;
- and
- the machine instruction employing a first register for input, the first register comprising an adjunct processor queue number field and a function code, the adjunct processor queue number field specifying a queue number of a selected queue to be processed, the queue being associated with an adjunct processor coupled to the central processing unit, and the function code designating an adjunct processor queue interruption control specifying an interruption control for the queue;
- and
- executing the machine instruction, the executing responsive to the function code designating the adjunct processor queue interruption control comprising:
- determining whether the queue is to be enabled for interrupts;
- and
- responsive to the determining indicating the queue is to be enabled for interrupts:
- setting an enablement indicator of the queue, the queue specified in the adjunct processor queue number field;
- and
- signaling to the adjunct processor that the queue is enabled for interrupts allowing the adjunct processor to generate an interrupt to the central processing unit for the queue.
10 more elements
A computer system for executing a machine instruction in a central processing unit, the computer system comprising:
- a memory;
- and
- a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
- obtaining, by the central processing unit, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
- an opcode field specifying a process adjunct processor queue instruction, the process adjunct processor queue instruction to enable or disable interrupts for a queue;
- and
- the machine instruction employing a first register for input, the first register comprising an adjunct processor queue number field and a function code, the adjunct processor queue number field specifying a queue number of a selected queue to be processed, the queue being associated with an adjunct processor coupled to the central processing unit, and the function code designating an adjunct processor queue interruption control specifying an interruption control for the queue;
- and
- executing the machine instruction, the executing responsive to the function code designating the adjunct processor queue interruption control comprising:
- determining whether the queue is to be enabled for interrupts;
- and
- responsive to the determining indicating the queue is to be enabled for interrupts:
- setting an enablement indicator of the queue, the queue specified in the adjunct processor queue number field;
- and
- signaling to the adjunct processor that the queue is enabled for interrupts allowing the adjunct processor to generate an interrupt to the central processing unit for the queue.
12 more elements
A method for executing a machine instruction in a central processing unit, the method comprising:
- obtaining, by the central processing unit, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
- an opcode field specifying a process adjunct processor queue instruction, the process adjunct processor queue instruction to enable or disable interrupts for a queue;
- and
- the machine instruction employing a first register for input, the first register comprising an adjunct processor queue number field and a function code, the adjunct processor queue number field specifying a queue number of a selected queue to be processed, the queue being associated with an adjunct processor coupled to the central processing unit, and the function code designating an adjunct processor queue interruption control specifying an interruption control for the queue;
- and
- executing the machine instruction, the executing responsive to the function code designating the adjunct processor queue interruption control comprising:
- determining whether the queue is to be enabled for interrupts;
- and
- responsive to the determining indicating the queue is to be enabled for interrupts:
- setting an enablement indicator of the queue, the queue specified in the adjunct processor queue number field;
- and
- signaling to the adjunct processor that the queue is enabled for interrupts allowing the adjunct processor to generate an interrupt to the central processing unit for the queue.
9 more elements
Dependencies are inferred from the claim text.