Electrical short locator method
AssigneeVerIC Systems LLC
InventorMikael Bo Lennart Sahrling
Life of this patent
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Abstract
A method for locating electrical shorts in layout designs by either systematically removing subcells in the layout hierarchy or, if the shorts are not found in any of the subcells, iteratively excluding portions of the top level layout from the electrical connectivity analysis and thereby locate the shorting polygons. Shorts existing both in subcells and the top level will be found by applying the method repeatedly until all shorts are located and eliminated.
Claims10
A method of finding a plurality of unwanted connections, hereafter referred to as shorts, between different electrical nodes in a physical layout of an integrated circuit, said layout comprising polygons and other geometrical shapes, hereafter referred to as polygons, and other cells known as subcells being part of a hierarchical layout, said method comprising:
- (a) reading layout design;
- (b) marking a user defined selection of polygons known to said user to belong to same electrical nodes;
- (c) determining if layout is hierarchical;
- (d) if said layout is hierarchical then removing all subcells from said layout and determining if said shorts are still present
- (1) if said shorts are still present searching for said shorts among said polygons by repeatedly excluding polygons in different parts of said layout from the electrical connectivity analysis until the group of polygons causing said shorts is identified;
- (2) if said shorts are not present then searching for said shorts among the subcells by repeatedly excluding different subcells from the electrical connectivity analysis until the subcells causing said shorts are identified;
- (e) if said layout is not hierarchical searching for said shorts among said polygons by repeatedly excluding polygons in different parts of said layout from the electrical connectivity analysis until the group of polygons causing said shorts is identified;
- whereby said shorts are found.
An apparatus for finding a plurality of unwanted connections, hereafter referred to as shorts, between different electrical nodes in a physical layout of an integrated circuit, said layout comprising polygons and other geometrical shapes, hereafter referred to as polygons, and other cells known as subcells being part of a hierarchical layout, said apparatus comprising a Central Processing Unit memory and input/output means, said apparatus further comprising:
- (a) input means for reading layout design;
- (b) means for marking a user defined selection of polygons known to said user to belong to same electrical nodes;
- (c) means for determining if layout is hierarchical;
- (d) if said layout is hierarchical then means for removing all subcells from said layout and means for determining if said shorts are still present
- (1) if said shorts are still present means for searching for said shorts among said polygons by repeatedly excluding polygons in different parts of said layout from the electrical connectivity analysis until the group of polygons causing said shorts is identified;
- (2) if said shorts are not present then means searching for said shorts among the subcells by repeatedly excluding different subcells from the electrical connectivity analysis until the subcells causing said shorts are identified;
- (e) if said layout is not hierarchical means for searching for said shorts among said polygons by repeatedly excluding polygons in different parts of said layout from the electrical connectivity analysis until the group of polygons causing said shorts is identified;
- whereby said shorts are found.
Dependencies are inferred from the claim text.