Architecture for local programming of quantum processor elements using latching qubits
AssigneeD-Wave Systems Inc.
InventorAndrew Joseph Berkley
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Abstract
An architecture for a quantum processor may include a set of superconducting flux qubits operated as computation qubits and a set of superconducting flux qubits operated as latching qubits. Latching qubits may include a first closed superconducting loop with serially coupled superconducting inductors, interrupted by a split junction loop with at least two Josephson junctions; and a clock signal input structure configured to couple clock signals to the split junction loop. Flux-based superconducting shift registers may be formed from latching qubits and sets of dummy latching qubits. The devices may include clock lines to clock signals to latch the latching qubits. Thus, latching qubits may be used to program and configure computation qubits in a quantum processor.
Claims24
A superconducting quantum processor comprising:
- a plurality of computation qubits, wherein each computation qubit comprises at least one loop of superconducting material and at least one Josephson junction, and wherein each computation qubit is configured to perform at least a portion of a computation;
- a plurality of latching qubits, wherein each latching qubit comprises a first loop of superconducting material and a compound Josephson junction that interrupts the first loop of superconducting material, the compound Josephson junction comprising a closed loop of superconducting material interrupted by at least two Josephson junctions, wherein the first loop of superconducting material and the compound Josephson junction form a closed superconducting current path, and wherein each latching qubit is configured to galvanically couple to at least one of a computation qubit and another latching qubit;
- and
- a clock signal input structure configured to couple clock signals to the compound Josephson junction of at least one latching qubit.
A superconducting system comprising:
- a computation qubit including at least one loop of superconducting material and at least one Josephson junction, wherein the computation qubit is configured to perform at least a portion of a computation;
- a signal input structure;
- and
- a latching qubit including a first loop of superconducting material and a compound Josephson junction that interrupts the first loop of superconducting material, the compound Josephson junction comprising a closed loop of superconducting material interrupted by at least two Josephson junctions, wherein the first loop of superconducting material and the compound Josephson junction form a closed superconducting current path, and wherein the compound Josephson junction of the latching qubit is communicatively coupleable to the signal input structure and the first loop of superconducting material of the latching qubit is communicatively coupleable to the computation qubit via a communicative coupling selected from the group consisting of inductive coupling and galvanic coupling.
A superconducting system comprising:
- a first computation qubit including at least one loop of superconducting material and at least one Josephson junction, wherein the first computation qubit is configured to perform at least a portion of a computation;
- and
- a superconducting shift register comprising a plurality of latching qubits arranged in a line of sequential coupling such that each latching qubit is inductively or galvanically coupled to at least one other adjacent latching qubit, wherein each respective latching qubit in the superconducting shift register includes a first loop of superconducting material and a compound Josephson junction that interrupts the first loop of superconducting material, the compound Josephson junction comprising a closed loop of superconducting material interrupted by at least two Josephson junctions, and wherein the first loop of superconducting material and the compound Josephson junction form a closed superconducting current path;
- wherein the compound Josephson junction of each respective latching qubit in the superconducting shift register is inductively or galvanically coupled to a respective signal input structure and a first one of the latching qubits in the superconducting shift register is inductively or galvanically coupled to the first computation qubit.
Dependencies are inferred from the claim text.