Advanced processor with mechanism for packet distribution at high line rate
AssigneeNetLogic Microsystems, Inc.
InventorDavid T. Hass
Life of this patent
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Abstract
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
Claims34
An advanced processor, comprising:
- a packet distribution engine (PDE) configured to receive a plurality of packets from a networking input and to provide the plurality of packets in a load-balanced distribution to a selected group of multiple threads;
- a plurality of processor cores configured to execute the multiple threads;
- a fast messaging network (FMN) having a ring based interconnect configuration, said FMN coupling the PDE to the plurality of processor cores, said FMN configured to link the plurality of processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory;
- and
- a data switch interconnect (DSI) separate from said FMN and having a ring based interconnect configuration, said DSI configured to link the plurality of processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory.
A method of controlling a flow of packets, the method comprising the steps of:
- receiving a plurality of packets from a networking input;
- placing the plurality of packets in a packet distribution engine (PDE);
- determining a selected group of multiple threads, the multiple threads being executable by a plurality of processor cores, the plurality of processor cores being directly coupled to the PDE;
- providing the plurality of packets from the PDE in a load-balanced distribution to the selected group of multiple threads via a fast messaging network (FMN) having a ring based interconnect configuration, said FMN directly coupling the PDE to the plurality of processor cores, said FMN configured to link the plurality of processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory;
- and
- passing information among the plurality of processor cores via a data switch interconnect (DSI), said DSI separate from said FMN and having a ring based interconnect configuration, said DSI configured to link the plurality of processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory.
An advanced processing system, comprising:
- a plurality of processor cores configured to execute multiple threads and to process a plurality of packets, the plurality of packets being received by a networking input, the plurality of packets being provided to the plurality of processor cores by a packet distribution engine (PDE), the plurality of packets being further provided in a load-balanced distribution to a selected group of the multiple threads;
- a fast messaging network (FMN) having a ring based interconnect configuration, said FMN coupling the PDE to the plurality of processor cores, said FMN configured to link the plurality of processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory;
- and
- a data switch interconnect (DSI) separate from said FMN and having a ring based interconnect configuration, said DSI configured to link the plurality of processor cores together such that each processor core has a data pathway to each of the other processor cores without going through memory.
Dependencies are inferred from the claim text.