Method of enabling the generation of reset signals in an integrated circuit

A method of enabling the generation of reset signals in an integrated circuit, the method comprising:

• receiving, in a design tool, information related to reset ports of a plurality of intellectual property cores;
• receiving, in the design tool, information related to a reset port of the integrated circuit;
• providing an intellectual property core comprising a reset circuit adapted to generate a plurality of reset signals for the plurality of intellectual property cores;
• and
• generating configuration data enabling programmable interconnects to couple a first reset signal of the plurality of reset signals to a first intellectual property core of the plurality of intellectual property cores and a second reset signal of the plurality of reset signals to a second intellectual property core of the plurality of intellectual property cores, and to couple the reset port of the integrated circuit to the reset circuit.

A method of enabling the generation of reset signals in an integrated circuit, the method comprising:

• receiving, in a design tool, information related to reset ports of a plurality of intellectual property cores;
• providing an intellectual property core comprising a reset circuit adapted to generate a first reset logic signal and a second reset signal for the plurality of intellectual property cores;
• generating configuration data enabling programmable interconnects to couple the first reset signal to a first intellectual property core of the plurality of intellectual property cores and the second reset signal to a second intellectual property core of the plurality of intellectual property cores;
• coupling the configuration data to the integrated circuit;
• and
• configuring the integrated circuit using the configuration data.