Method and system for performing sequential equivalence checking on integrated circuit (IC) designs

A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for performing sequential equivalence checking between integrated circuit (IC) designs, the method comprising:

• receiving a first IC design and a second IC design, wherein each of the first and second IC designs comprises a top design level and a bottom design level, and wherein the bottom design levels comprise one or more sub-blocks within the corresponding top design levels;
• verifying if each of the sub-blocks in the bottom design level of the first design is conditionally equivalent to a corresponding sub-block in the bottom design level of the second design, wherein two designs are conditionally equivalent if the two designs can become sequentially equivalent by adding registers on the input and output ports of the two designs;
• verifying if the top design level of the first design is conditionally equivalent to the top design level of the second design;
• verifying if the first design is temporally equivalent to the second design;
• and
• if the preceding verifications are true, determining that the first design and the second design are sequentially equivalent.

A system that performs sequential equivalence checking between integrated circuit (IC) designs, comprising:

• a processor;
• a memory;
• a receiving mechanism configured to receive a first IC design and a second IC design, wherein each of the first and second IC designs comprises a top design level and a bottom design level, and wherein the bottom design levels comprise one or more sub-blocks within the corresponding top design levels;
• a verification mechanism configured to verify if each of the sub-blocks in the bottom design level of the first design is conditionally equivalent to a corresponding sub-block in the bottom design level of the second design, wherein two designs are conditionally equivalent if the two designs can become sequentially equivalent by adding registers on the input and output ports of the two designs;
• and
• wherein the verification mechanism is further configured to:
• verify if the top design level of the first design is conditionally equivalent to the top design level of the second design;
• and
• verify if the first design is temporally equivalent to the second design;
• and
• determine that the first design and the second design are sequentially equivalent if the preceding verifications are true.