US 8,015,520 B2 · Methods and apparatuses for automated circuit optimization and verification

Abstract

Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and verification. In one embodiment, a hierarchical block is optimized and transformed during design synthesis using one or more lemmas at the boundary of the hierarchical block. For example, the lemmas are automatically generated to specify range information for input boundary nodes. The lemmas are also used for the equivalence checker to perform hierarchical equivalence checking. Equivalence of hierarchical blocks is individually checked, in view of the lemmas. Thus, based on the lemmas, optimizations across hierarchical boundaries can be performed, while the hierarchical structure of the design is preserved so that equivalence checking of hierarchical circuit designs can still be based on the equivalence of individual hierarchical blocks.

Claims22

Dependent claims

A non-transitory machine readable storage medium containing executable computer program instructions which when executed by a digital processing system cause said system to perform a method to design a circuit with a plurality of portions, the method comprising:

automatically generating, by a processor, at least one lemma that specifies one or more conditions across one or more boundaries of the plurality of portions of the circuit;
individually transforming the plurality of portions of the circuit from a first design into a second design using the at least one lemma;
and
exporting the at least one lemma for use by one or more application processes.

1 more element

Dependencies are inferred from the claim text.

Methods and apparatuses for automated circuit optimization and verification

Life of this patent

Methods and apparatuses for automated circuit optimization and verification

Life of this patent

Abstract

Claims22