System and method for creating a logical representation of a functional logic system from a physical representation

A computer system comprising:

• a processing module;
• and
• a database module comprising a rule library module and a non-transitory instruction module encoded with instructions which when executed cause the processing module to perform the steps of:
• loading a physical hardware description language (HDL) representation of the system and creating a physical HDL representation from a physical schematic of the system;
• identifying from the physical HDL representation power nets and component blocks, loading from the rule library initial condition rules for the power nets and the component blocks, and assigning the initial condition rules to the power nets and component blocks;
• and
• using at least in part the initial condition rules to transform the physical HDL representation to a logical HDL representation by
• identifying connector blocks and converting the connector blocks to hierarchical IO logical HDL representations;
• identifying component blocks appropriate for conversion to logical instantiations and converting the appropriate component blocks to logical HDL representations;
• identifying component blocks appropriate for deletion and deleting the component blocks appropriate for deletion;
• and
• identifying resistor components and converting resistor components to logical HDL representations.

An article of manufacture including a non-transitory data storage medium, said non-transitory data storage medium including a set of machine-readable instructions that are executable by a processing device to implement an algorithm, said algorithm comprising the steps of:

• loading a physical hardware description language (HDL) representation of the system and creating a physical HDL representation from a physical schematic of the system;
• identifying from the physical HDL representation power nets and component blocks, loading from a rule library initial condition rules for the power nets and the component blocks, and assigning the initial condition rules to the power nets and component blocks;
• and
• using at least in part the initial condition rules to transform the physical HDL representation to a logical HDL representation by
• identifying connector blocks and converting the connector blocks to hierarchical IO logical HDL representations;
• identifying component blocks appropriate for conversion to logical instantiations and converting the appropriate component blocks to logical HDL representations;
• identifying component blocks appropriate for deletion and deleting the component blocks appropriate for deletion;
• and
• identifying resistor components and converting resistor components to logical HDL representations.