Display designing system and method for designing a display

A display designing system applied to a data processing device having an input circuit for inputting initial parameters, selecting operation type parameters and selecting output form parameters and an output circuit for displaying output results, the displaying designing system comprising:

• a capacitor charging operation circuit for performing operations in accordance with a first operation rule after receiving the initial parameters input to the input circuit, to generating a first operation result about capacitor charging;
• a potential holding operation circuit for performing operations in accordance with a second operation rule after receiving the initial parameters input to the input circuit, to generate a second operation result about potential holding;
• a asymmetric kickback operation circuit for performing operations in accordance with a third operation rule after receiving the initial parameters input to the input circuit, to generate a third operation result about asymmetric kickback;
• a signal delaying operation circuit for performing operations in accordance with a fourth operation rule after receiving the initial parameters input to the input circuit, to generate a fourth operation result about signal delaying;
• and
• an integration circuit for receiving the first operation result from the capacitor charging operation circuit, the second operation result from the potential holding operation circuit, the third operation result from the asymmetric kickback operation circuit and the fourth operation result from the signal delaying operation circuit, and comparing the first operation result, the second operation result, the third operation result and the fourth operation result in accordance with the selected operation type parameters and the selected output form parameters, to generate a correspondence relation of the first operation result, the second operation result, the third operation result and the fourth operation result and transfer the first operation result, the second operation result, the third operation result, the fourth operation result and the correspondence relation to the output circuit;
• wherein the first operation rule of the capacitor charging operation circuit comprises the following equation:
• (
• W
• L
• )
• charge
• ,
• FSC
• ≅
• 9
• ⁢
• (
• 1
• +
• ɛ
• insu
• ⁢
• d
• LC
• t
• insu
• ⁢
• ɛ
• LC
• ⁢
• h
• FSC
• 1
• +
• ɛ
• insu
• ⁢
• d
• LC
• t
• insu
• ⁢
• ɛ
• LC
• ⁢
• h
• CF
• )
• ⁢
• (
• W
• L
• )
• charge
• ,
• CF
• ,
• where W is a channel width of a pixel transistor, L is a channel length of the pixel transistor, ∈insu is a dielectric constant of an insulation layer of a field effect transistor, tinsu is a thickness of the insulation layer of a field effect transistor, DLC is a thickness of a liquid crystal layer of the field effect transistor, ∈LC is a dielectric constant of the liquid crystal layer of the field effect transistor, h=Acs/Apixel is an area ratio between a storage capacitor and a pixel, (W/L)charge,CF is a width-to-length ratio between a channel width and a channel length of a field effect transistor of a color-filter display, and (W/L)charge,FSC is another width-to-length ratio between a channel width and a channel length of a field effect of a field-sequential color display having the same resolution and screen size as the color-filter display.