Symbol rate hardware accelerator

A hardware accelerator for performing channel processing on information bits for wireless transmission and reception, the hardware accelerator being in communication with a shared memory, the hardware accelerator comprising:

• a first buffer and a second buffer for storing the information bits and processed information bits;
• at least one address generator for generating an address for accessing the first buffer and the second buffer;
• a translation read-only memory (ROM) for generating a translated address for accessing the first buffer and the second buffer;
• an interface for accessing the shared memory;
• a cyclic redundancy check (CRC) generator for performing a block coding on one of the information bits and the processed information bits to generate parity bits;
• a convolutional encoder for performing convolutional encoding on one of the information bits and the processed information bits;
• and
• a controller configured to generate control signals to set parameters for the CRC generator, the convolutional encoder and the address generator, and perform a predefined sequence of control commands for channel processing on the information bits by manipulating the information bits and the processed information bits while moving the information bits and the processed information bits between the first buffer and the second buffer back and forth, wherein moving data between the buffers includes moving the data through one of the shared memory, the cyclic redundancy check, CRC, generator, and the convolutional encoder, and manipulating the data in accordance with a control word to perform a specific function.