Decompressors for low power decompression of test patterns
AssigneeMentor Graphics Corporation
InventorsJanusz Rajski, Grzegorz Mrugalski, Dariusz Czysz, Jerzy Tyszer
Life of this patent
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Abstract
Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
Claims20
A method, comprising:
- inputting compressed test pattern bits;
- generating decompressed test pattern bits from the compressed test pattern bits;
- storing the decompressed test pattern bits in one or more registers;
- and
- loading scan chains of a circuit-under-test with the decompressed test pattern bits stored in the one or more registers, the loading being performed for two or more scan chain shift cycles such that the decompressed test pattern bits stored in the one or more registers are repeatedly loaded into the scan chain.
A system, comprising:
- means for generating decompressed test pattern bits from compressed test pattern bits;
- and
- means for storing the decompressed test pattern bits and for loading scan chains of a circuit-under-test with the stored decompressed test pattern bits for two or more scan chain shift cycles such that the stored decompressed test pattern bits are repeatedly loaded into the scan chain.
One or more tangible computer-readable media storing computer-executable instructions which when executed by a computer will cause the computer to perform a method, the method comprising:
- creating circuit design information representing a test pattern decompression circuit for a circuit, the test pattern decompression circuit being configured to perform a method comprising,
- inputting compressed test pattern bits;
- generating decompressed test pattern bits from the compressed test pattern bits;
- storing the decompressed test pattern bits in one or more registers;
- and
- loading scan chains of the circuit with the decompressed test pattern bits stored in the one or more registers, the loading being performed for two or more scan chain shift cycles such that the decompressed test pattern bits stored in the one or more registers are repeatedly loaded into the scan chain.
Dependencies are inferred from the claim text.