Redundancy circuit and semiconductor memory device

A method comprising:

• comparing an input address with a first redundancy address to output a first redundancy selection signal, the first redundancy selection signal takes an active level when the input address is coincident with the first redundancy address and takes an inactive level when the input address is incoincident with the first redundancy address;
• comparing the input address with a second redundancy address to output a second redundancy selection signal, the second redundancy selection signal takes an active level when the input address is coincident with the second redundancy address and takes an inactive level when the input address is incoincident with the second redundancy address;
• comparing the input address with a third redundancy address to output a third redundancy selection signal, the third redundancy selection signal takes an active level when the input address is coincident with the third redundancy address and takes an inactive level when the input address is incoincident with the third redundancy address;
• producing a first error signal that takes an active level when the first redundancy selection signal takes the inactive level and the second redundancy selection signal takes the active level and an inactive level when the first redundancy selection signal takes the active level and the second redundancy selection signal takes the inactive level, or when each of the first and second redundancy selection signals takes the active level, or when each of the first and second redundancy selection signals takes the inactive level;
• producing a second error signal that takes an active level when the second redundancy selection signal takes the inactive level and the third redundancy selection signal takes the active level and an inactive level when the second redundancy selection signal takes the active level and the third redundancy selection signal takes the inactive level, or when each of the second and third redundancy selection signals takes the active level, or when each of the second and third redundancy selection signals takes the inactive level;
• and
• detecting a main error when at least one of the first and second error signals takes the active level.

A method comprising;

• initializing a first signal to take a first level;
• comparing an input address with a first address to change the first signal from the first level to a second level when the input address is coincident with the first address and maintain the first signal at the first level when the input address is incoincident with the first address;
• comparing the input address with a second address to produce a second signal that takes a first state when the input address is coincident with the second address and takes a second state when the input address is incoincident with the second address;
• producing a third signal in response to the first and second signals, the third signal taking an inactive level when the first signal takes the second level, the third signal further taking the inactive level when the first signal takes the first level and the second signal takes the second state, and the third signal taking an active level when the first signal takes the first level and the second signal takes the first state, whereby the third signal takes the inactive level when the input address takes the first address prior to the second address and the active level when the input address takes the second address prior to the first address;
• initializing a fourth signal to take a first level;
• changing the fourth signal from the first level to the second level when the input address is coincident with the second address and maintain the fourth signal at the first level when the input address is incoincident with the second address;
• comparing the input address with a third address to produce a fifth signal that takes the first state when the input address is coincident with the third address and takes the second state when the input address is incoincident with the third address;
• and
• producing a sixth signal in response to the fourth and fifth signals, the sixth signal taking the inactive level when the fourth signal takes the second level, the sixth signal further taking the inactive level when the fourth signal takes the first level and the fifth signal takes the second state, and the sixth signal taking the active level when the fourth signal takes the first level and the fifth signal takes the first state, whereby the sixth signal takes the inactive level when the input address takes the second address prior to the third address and the active level when the input address takes the third address prior to the second address.