Processor debugging apparatus and processor debugging method
AssigneeFujitsu Limited
InventorsHideo Yamashita, Ryuji Kan
Life of this patent
Estimating the term…
Abstract
A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.
Claims13
A processor debugging apparatus in a debugged processor executing a plurality of operation codes, the processor debugging apparatus comprising:
- an operation controller that controls the executing of the plurality of operation codes by the debugged processor and generates a valid signal associated with the executing;
- a shift register that stores the plurality of operation codes executed in the debugged processor for multiple clock cycles when the valid signal is inputted into the shift register from the operation controller;
- a signal reading unit that scans and reads out the values of the executed operation codes in the shift register;
- a timing designating unit that designates a timing for storing each of the executed operation codes in the shift register;
- and
- a timing memory unit that stores a timing value for identifying a timing designated by the timing designating unit, in association with each of the executed operation codes to be stored in the shift register.
A processor debugging method for a debugged processor executing a plurality of operation codes, the processor debugging method comprising:
- controlling the executing of the plurality of operation codes by the debugged processor;
- generating a valid signal associated with the executing;
- storing a plurality of executed operation codes into a shift register for multiple clock cycles when the valid signal generated at the generating is inputted into the shift register;
- scanning and reading out the plurality of executed operation codes stored in the shift register;
- and
- recording a timing value for identifying a timing in association with each of the executed operation codes to be stored in the shift register.
A processor debugging method for a processor executing a plurality of operation codes, the processor debugging method comprising:
- controlling the executing of the plurality of operation codes by the debugged processor;
- generating a valid signal associated with the executing;
- storing a plurality of executed operation codes into a shift register for multiple clock cycles when the valid signal generated at the generating is inputted into the shift register;
- and
- executing a debugging operation by determining sequential transition statuses of the plurality of executed operation codes over the multiple clock cycles by reading the plurality of executed operation codes stored in the shift register.
Dependencies are inferred from the claim text.