Memory circuit
AssigneeQimonda AG
InventorsMichael Bruennert, Christoph Bilger, Peter Gregorius, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
Life of this patent
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Abstract
The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.
Claims21
A memory circuit, comprising:
- a plurality of storage cells for storing data;
- a plurality of redundant spare storage cells for replacing defective storage cells;
- and
- a memory access logic for accessing said plurality of storage cells connected to at least one replacement setting register, said at least one replacement setting register being writeable during operation of said memory circuit to store a plurality of replacement settings, wherein each of said plurality of replacement settings comprises:
- first information data about a location of a storage cell cluster having at least one defective storage cell;
- and
- second information data about a location of a spare storage cell cluster replacing said storage cluster, the second information data being different than the first information data.
A memory circuit comprising:
- a plurality of storage cells for storing data;
- a plurality of redundant spare storage cells for replacing defective storage cells;
- and
- at least one writeable replacement setting register for storing replacement settings, wherein each of said replacement settings comprises:
- first information data about a location of a storage cell cluster having at least one defective storage cell;
- and
- second information data about a location of a spare storage cell cluster replacing said storage cluster, the second information data being different than the first information data.
A method for in-operation memory repair of a memory circuit comprising the steps of:
- (a) performing a failure mapping to determine updated replacement settings depending on the location of defective storage cells detected during operation of said memory circuit and depending on replacement settings already stored in a replacement setting register of said memory circuit;
- (b) saving data stored in storage cells to be replaced according to the updated replacement settings by redundant spare storage cells into a temporary data storage;
- (c) writing the updated replacement settings in said replacement setting register;
- and
- (d) writing the saved data from the temporary data storage to the redundant spare storage cells indicated by the updated replacement settings,
- wherein said replacement settings comprise:
- information data about a location of a storage cell cluster having at least one defective storage cell;
- and
- information data about a location of a spare storage cell cluster replacing said storage cluster.
A method for memory repair of a memory circuit during a boot-up of said memory circuit comprising the steps of:
- (a) performing a boot-up memory test and deriving a failure mapping on the basis of failure information provided by said boot-up memory test to determine updated replacement settings depending on the location of defective storage cells detected during a boot-up test of said memory circuit and depending on replacement settings loaded from a non-volatile storage, wherein said replacement settings comprise information data about a location of a storage cell cluster having at least one defective storage cell and information data about a location of a spare storage cell cluster replacing said storage cluster;
- and
- (b) writing the updated replacement settings to a replacement setting register of said memory circuit.
Dependencies are inferred from the claim text.