Clock and data recovery (CDR) method and apparatus
AssigneeIntel Corporation
InventorsGanesh Balamurugan, Frank P. O'Mahony, Bryan K. Casper
Life of this patent
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Abstract
Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
Claims20
A method for recovering data from an input data stream of a device, comprising:
- synchronizing, during an initialization phase of the device, a data clock (DCK) with an input data stream;
- synchronizing, during the initialization phase, an edge clock (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK;
- and
- sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK, including generating a transition level reference voltage for maintaining synchronization during a subsequent normal operation phase.
An apparatus for recovering a clock and data from an input data stream, comprising:
- a data clock phase selector configured to synchronize a data clock (DCK) with an input data stream;
- an edge clock phase selector configured to synchronize an edge clock (ECK) with the input data stream;
- a sampling circuit coupled to the edge clock phase selector and configured to sample a rising edge of the input data stream with the ECK to generate a transition level reference voltage;
- and
- a controller coupled to the data clock phase selector and the edge clock phase selector, including logic configured to control the data clock phase selector and the edge clock phase selector to synchronize the DCK and the ECK with the input data stream respectively, during an initialization phase, such that the ECK is in a target phase relationship with the DCK.
A system, comprising:
- a bus;
- and
- a bus agent coupled to the bus, the bus agent having:
- a data clock phase selector configured to synchronize a data clock (DCK) with an input data stream received from the bus;
- an edge clock phase selector configured to synchronize an edge clock (ECK) with the input data stream;
- a sampling circuit coupled to the edge clock phase selector and configured to sample a rising edge of the input data stream with the ECK to generate a transition level reference voltage;
- and
- a controller coupled to the data clock phase selector and the edge clock phase selector, including logic configured to control the data clock phase selector and the edge clock phase selector to synchronize the DCK and the ECK with the input data stream respectively, such that the ECK is in a target phase relationship with the DCK.
Dependencies are inferred from the claim text.